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Merge pull request #114 from negativeExponent/mesenx
fix warnings
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Original file line number | Diff line number | Diff line change |
---|---|---|
@@ -0,0 +1,69 @@ | ||
#pragma once | ||
#include "stdafx.h" | ||
#include "BaseMapper.h" | ||
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class Mapper500 : public BaseMapper | ||
{ | ||
private: | ||
uint8_t _regs[2]; | ||
uint8_t _latch; | ||
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protected: | ||
virtual uint16_t GetPRGPageSize() override { return 0x4000; } | ||
virtual uint16_t GetCHRPageSize() override { return 0x2000; } | ||
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uint32_t GetWorkRamSize() override { return 0x2000; } | ||
uint32_t GetWorkRamPageSize() override { return 0x1000; } | ||
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void InitMapper() override | ||
{ | ||
_regs[0] = 0; | ||
_regs[1] = 0; | ||
_latch = 0; | ||
AddRegisterRange(0x6000, 0x6FFF, MemoryOperation::Write); | ||
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UpdateState(); | ||
} | ||
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void Reset(bool softReset) override | ||
{ | ||
if(!softReset) { | ||
_latch = 0; | ||
} | ||
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_regs[0] = 0; | ||
_regs[1] = 0; | ||
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UpdateState(); | ||
} | ||
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void StreamState(bool saving) override | ||
{ | ||
BaseMapper::StreamState(saving); | ||
Stream(_regs[0], _regs[1], _latch); | ||
} | ||
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void UpdateState() | ||
{ | ||
uint16_t outerBank = (_regs[0] & 0x0F) << 3; | ||
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SetCpuMemoryMapping(0x7000, 0x7FFF, 0, PrgMemoryType::WorkRam); | ||
SelectPRGPage(0, outerBank | (_latch & 0x07)); | ||
SelectPRGPage(1, outerBank | 0x07); | ||
SelectCHRPage(0, 0); | ||
SetMirroringType((_regs[1] & 0x01) ? MirroringType::Vertical : MirroringType::Horizontal); | ||
} | ||
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||
void WriteRegister(uint16_t addr, uint8_t value) override | ||
{ | ||
if(addr < 0x8000) { | ||
if((_regs[1] & 0x80) == 0) { | ||
_regs[addr & 0x01] = value; | ||
} | ||
} else { | ||
_latch = value; | ||
} | ||
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||
UpdateState(); | ||
} | ||
}; |
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Original file line number | Diff line number | Diff line change |
---|---|---|
@@ -0,0 +1,68 @@ | ||
#pragma once | ||
#include "stdafx.h" | ||
#include "BaseMapper.h" | ||
|
||
class Mapper501 : public BaseMapper | ||
{ | ||
private: | ||
uint8_t _regs[2]; | ||
uint8_t _latch; | ||
|
||
protected: | ||
virtual uint16_t GetPRGPageSize() override { return 0x8000; } | ||
virtual uint16_t GetCHRPageSize() override { return 0x2000; } | ||
|
||
uint32_t GetWorkRamSize() override { return 0x2000; } | ||
uint32_t GetWorkRamPageSize() override { return 0x1000; } | ||
|
||
void InitMapper() override | ||
{ | ||
_regs[0] = 0; | ||
_regs[1] = 0; | ||
_latch = 0; | ||
AddRegisterRange(0x6000, 0x6FFF, MemoryOperation::Write); | ||
|
||
UpdateState(); | ||
} | ||
|
||
void Reset(bool softReset) override | ||
{ | ||
if(!softReset) { | ||
_latch = 0; | ||
} | ||
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||
_regs[0] = 0; | ||
_regs[1] = 0; | ||
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UpdateState(); | ||
} | ||
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||
void StreamState(bool saving) override | ||
{ | ||
BaseMapper::StreamState(saving); | ||
Stream(_regs[0], _regs[1], _latch); | ||
} | ||
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void UpdateState() | ||
{ | ||
uint16_t outerBank = (_regs[0] & 0x0F) << 2; | ||
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SetCpuMemoryMapping(0x7000, 0x7FFF, 0, PrgMemoryType::WorkRam); | ||
SelectPRGPage(0, outerBank + (_latch & 0x07)); | ||
SelectCHRPage(0, 0); | ||
SetMirroringType((_latch & 0x10) ? MirroringType::ScreenBOnly : MirroringType::ScreenAOnly); | ||
} | ||
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void WriteRegister(uint16_t addr, uint8_t value) override | ||
{ | ||
if(addr < 0x8000) { | ||
if((_regs[1] & 0x80) == 0) { | ||
_regs[addr & 0x01] = value; | ||
} | ||
} else { | ||
_latch = value; | ||
} | ||
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||
UpdateState(); | ||
} | ||
}; |
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Original file line number | Diff line number | Diff line change |
---|---|---|
@@ -0,0 +1,80 @@ | ||
#pragma once | ||
#include "stdafx.h" | ||
#include "BaseMapper.h" | ||
|
||
class Mapper502 : public BaseMapper | ||
{ | ||
private: | ||
uint8_t _regs[2]; | ||
uint8_t _latch; | ||
|
||
protected: | ||
virtual uint16_t GetPRGPageSize() override { return 0x4000; } | ||
virtual uint16_t GetCHRPageSize() override { return 0x2000; } | ||
|
||
uint32_t GetWorkRamSize() override { return 0x2000; } | ||
uint32_t GetWorkRamPageSize() override { return 0x1000; } | ||
|
||
void InitMapper() override | ||
{ | ||
_regs[0] = 0; | ||
_regs[1] = 0; | ||
_latch = 0; | ||
AddRegisterRange(0x6000, 0x6FFF, MemoryOperation::Write); | ||
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UpdateState(); | ||
} | ||
|
||
void Reset(bool softReset) override | ||
{ | ||
if(!softReset) { | ||
_latch = 0; | ||
} | ||
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_regs[0] = 0; | ||
_regs[1] = 0; | ||
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UpdateState(); | ||
} | ||
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void StreamState(bool saving) override | ||
{ | ||
BaseMapper::StreamState(saving); | ||
Stream(_regs[0], _regs[1], _latch); | ||
} | ||
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void UpdateState() | ||
{ | ||
uint16_t outerBank; | ||
uint16_t mask = (8 << ((_regs[1] >> 4) & 0x03)) - 1; | ||
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SetCpuMemoryMapping(0x7000, 0x7FFF, 0, PrgMemoryType::WorkRam); | ||
if(_regs[1] & 0x06) { | ||
outerBank = (_regs[0] & 0x0F) << 2; | ||
SelectPrgPage2x(0, (outerBank + (_latch & (mask >> 1))) << 1); | ||
} else { | ||
outerBank = (_regs[0] & 0x0F) << 3; | ||
SelectPRGPage(0, outerBank + (_latch & mask)); | ||
SelectPRGPage(1, outerBank + mask); | ||
} | ||
SelectCHRPage(0, 0); | ||
if(_regs[1] & 0x02) { | ||
SetMirroringType((_latch & 0x10) ? MirroringType::ScreenBOnly : MirroringType::ScreenAOnly); | ||
} else { | ||
SetMirroringType((_regs[1] & 0x01) ? MirroringType::Vertical : MirroringType::Horizontal); | ||
} | ||
} | ||
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void WriteRegister(uint16_t addr, uint8_t value) override | ||
{ | ||
if(addr < 0x8000) { | ||
if((_regs[1] & 0x80) == 0) { | ||
_regs[addr & 0x01] = value; | ||
} | ||
} else { | ||
_latch = value; | ||
} | ||
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UpdateState(); | ||
} | ||
}; |
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