Add support for setting serial port switch control register from device tree

Documentation/devicetree/bindings/arm/cpu-enable-method/nuvoton,npcm7xx-smp

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+=========================================================
+Secondary CPU enable-method "nuvoton,npcm7xx-smp" binding
+=========================================================
+
+To apply to all CPUs, a single "nuvoton,npcm7xx-smp" enable method should be
+defined in the "cpus" node.
+
+Enable method name:	"nuvoton,npcm7xx-smp"
+Compatible machines:	"nuvoton,npcm750"
+Compatible CPUs:	"arm,cortex-a9"
+Related properties:	(none)
+
+Note:
+This enable method needs valid nodes compatible with "arm,cortex-a9-scu" and
+"nuvoton,npcm750-gcr".
+
+Example:
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		enable-method = "nuvoton,npcm7xx-smp";
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a9";
+			clocks = <&clk NPCM7XX_CLK_CPU>;
+			clock-names = "clk_cpu";
+			reg = <0>;
+			next-level-cache = <&L2>;
+		};
+
+		cpu@1 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a9";
+			clocks = <&clk NPCM7XX_CLK_CPU>;
+			clock-names = "clk_cpu";
+			reg = <1>;
+			next-level-cache = <&L2>;
+		};
+	};
+

Documentation/devicetree/bindings/arm/npcm/npcm.txt

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+NPCM Platforms Device Tree Bindings
+-----------------------------------
+NPCM750 SoC
+Required root node properties:
+	- compatible = "nuvoton,npcm750";
+
+Optional root node properties:
+	- nuvoton,npcm750-spswc : value of serial ports switch control register

Documentation/devicetree/bindings/clock/nuvoton,npcm750-clk.txt

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+* Nuvoton NPCM7XX Clock Controller
+
+Nuvoton Poleg BMC NPCM7XX contains an integrated clock controller, which
+generates and supplies clocks to all modules within the BMC.
+
+External clocks:
+
+There are six fixed clocks that are generated outside the BMC. All clocks are of
+a known fixed value that cannot be changed. clk_refclk, clk_mcbypck and
+clk_sysbypck are inputs to the clock controller.
+clk_rg1refck, clk_rg2refck and clk_xin are external clocks suppling the
+network. They are set on the device tree, but not used by the clock module. The
+network devices use them directly.
+Example can be found below.
+
+All available clocks are defined as preprocessor macros in:
+dt-bindings/clock/nuvoton,npcm7xx-clock.h
+and can be reused as DT sources.
+
+Required Properties of clock controller:
+
+	- compatible: "nuvoton,npcm750-clk" : for clock controller of Nuvoton
+		  Poleg BMC NPCM750
+
+	- reg: physical base address of the clock controller and length of
+		memory mapped region.
+
+	- #clock-cells: should be 1.
+
+Example: Clock controller node:
+
+	clk: clock-controller@f0801000 {
+		compatible = "nuvoton,npcm750-clk";
+		#clock-cells = <1>;
+		reg = <0xf0801000 0x1000>;
+		clock-names = "refclk", "sysbypck", "mcbypck";
+		clocks = <&clk_refclk>, <&clk_sysbypck>, <&clk_mcbypck>;
+	};
+
+Example: Required external clocks for network:
+
+	/* external reference clock */
+	clk_refclk: clk-refclk {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <25000000>;
+		clock-output-names = "refclk";
+	};
+
+	/* external reference clock for cpu. float in normal operation */
+	clk_sysbypck: clk-sysbypck {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <800000000>;
+		clock-output-names = "sysbypck";
+	};
+
+	/* external reference clock for MC. float in normal operation */
+	clk_mcbypck: clk-mcbypck {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <800000000>;
+		clock-output-names = "mcbypck";
+	};
+
+	 /* external clock signal rg1refck, supplied by the phy */
+	clk_rg1refck: clk-rg1refck {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <125000000>;
+		clock-output-names = "clk_rg1refck";
+	};
+
+	 /* external clock signal rg2refck, supplied by the phy */
+	clk_rg2refck: clk-rg2refck {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <125000000>;
+		clock-output-names = "clk_rg2refck";
+	};
+
+	clk_xin: clk-xin {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <50000000>;
+		clock-output-names = "clk_xin";
+	};
+
+
+Example: GMAC controller node that consumes two clocks: a generated clk by the
+clock controller and a fixed clock from DT (clk_rg1refck).
+
+	ethernet0: ethernet@f0802000 {
+		compatible = "snps,dwmac";
+		reg = <0xf0802000 0x2000>;
+		interrupts = <0 14 4>;
+		interrupt-names = "macirq";
+		clocks	= <&clk_rg1refck>, <&clk NPCM7XX_CLK_AHB>;
+		clock-names = "stmmaceth", "clk_gmac";
+	};

Documentation/devicetree/bindings/hwmon/npcm7xx-fan.txt

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+Nuvoton NPCM7xx fan tachometer (Fan) controller device driver
+
+The NPCM7xx fan tachometer controller supports upto 16 Fan inputs.
+
+Required properties:
+- compatible      : "nuvoton,npcm750-fan" for Poleg NPCM750.
+- reg             : Offset and length of the register set for the device.
+- clocks          : phandle of fan reference clock.
+- interrupts      : Contain the fan interrupts with flags for
+                    falling edge.
+
+fan: fan@0 {
+	compatible = "nuvoton,npcm750-fan";
+	reg = <0xf0180000 0x8000>;
+	interrupts = <0 96 4>, <0 97 4>, <0 98 4>, <0 99 4>,
+		<0 100 4>, <0 101 4>, <0 102 4>, <0 103 4>;
+	clocks = <&clk NPCM7XX_CLK_APB4>;
+};

Documentation/devicetree/bindings/hwmon/npcm7xx-pwm.txt

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+Nuvoton NPCM7xx Pulse-width modulation (PWM) controller device driver
+
+The NPCM7xx PWM controller supports upto 8 PWM outputs.
+Each PWM output module have watchdog.
+
+Required properties:
+- compatible      : "nuvoton,npcm750-pwm" for Poleg NPCM750.
+- reg             : Offset and length of the registers set for the device.
+- clocks          : phandle of pwm reference clock.
+
+pwm:pwm@f0103000 {
+	compatible = "nuvoton,npcm750-pwm";
+	reg = <0xf0103000 0x1000
+				0xf0104000 0x1000>;
+	clocks = <&clk NPCM7XX_CLK_APB3>;
+};

Documentation/devicetree/bindings/i2c/i2c-npcm7xx.txt

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+Nuvoton NPCM7XX I2C bus
+
+The NPCM750x includes sixteen I2C busses
+
+Required properties:
+- compatible      : "nuvoton,npcm750-i2c-bus" for Poleg NPCM750.
+- reg             : Offset and length of the register set for the device.
+- interrupts      : Contain the I2C interrupt with flags for falling edge.
+- clocks          : phandle of I2C reference clock.
+
+Optional:
+- bus-frequency   : Contain the I2C bus frequency,
+					the defualt I2C bus frequency is 100000.
+
+Example:
+
+i2c0: i2c-bus@f0080000 {
+	reg = <0xf0080000 0x1000>;
+	compatible = "nuvoton,npcm750-i2c-bus";
+	clocks = <&clk NPCM7XX_CLK_APB2>;
+	bus-frequency = <100000>;
+	interrupts = <0 64 4>;
+};

Documentation/devicetree/bindings/iio/adc/npcm7xx-adc.txt

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+Nuvoton NPCM7XX Analog to Digital Converter (ADC)
+
+The NPCM7XX ADC is a 10-bit converter for eight channel inputs,
+The ADC module includes an eight-to-one multiplexer.
+
+Required properties:
+- compatible      : "nuvoton,npcm750-adc" for Poleg NPCM750.
+- reg             : Offset and length of the register set for the device.
+
+Required clocking property, have to be one of:
+- clocks          : phandle of timer reference clock.
+- clock-names	  : Must contain "clk_adc", matching entry in the clocks property.
+- vref			  : ADC Reference voltage, defualt 2048.
+
+Example:
+
+adc: adc@f000c000 {
+	compatible = "nuvoton,npcm750-adc";
+	reg = <0xf000c000 0x1000>;
+	clocks = <&clk NPCM7XX_CLK_ADC>;
+	clock-names = "clk_adc";
+	vref = <2048>;
+};

Documentation/devicetree/bindings/ipmi/aspeed-kcs-bmc.txt

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+* Aspeed KCS (Keyboard Controller Style) IPMI interface
+
+The Aspeed SOCs (AST2400 and AST2500) are commonly used as BMCs
+(Baseboard Management Controllers) and the KCS interface can be
+used to perform in-band IPMI communication with their host.
+
+Required properties:
+- compatible : should be one of
+    "aspeed,ast2400-kcs-bmc"
+    "aspeed,ast2500-kcs-bmc"
+- interrupts : interrupt generated by the controller
+- kcs_chan : The LPC channel number in the controller
+- kcs_addr : The host CPU IO map address
+
+
+Example:
+
+    kcs3: kcs3@0 {
+        compatible = "aspeed,ast2500-kcs-bmc";
+        reg = <0x0 0x80>;
+        interrupts = <8>;
+        kcs_chan = <3>;
+        kcs_addr = <0xCA2>;
+        status = "okay";
+    };

Documentation/devicetree/bindings/ipmi/npcm7xx-kcs-bmc.txt

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+* Nuvoton NPCM7xx KCS (Keyboard Controller Style) IPMI interface
+
+The Nuvoton SOCs (NPCM7xx) are commonly used as BMCs
+(Baseboard Management Controllers) and the KCS interface can be
+used to perform in-band IPMI communication with their host.
+
+Required properties:
+- compatible : should be one of
+    "nuvoton,npcm750-kcs-bmc"
+- interrupts : interrupt generated by the controller
+- kcs_chan : The KCS channel number in the controller
+
+Example:
+
+    lpc_kcs: lpc_kcs@f0007000 {
+        compatible = "nuvoton,npcm750-lpc-kcs", "simple-mfd", "syscon";
+        reg = <0xf0007000 0x40>;
+        reg-io-width = <1>;
+
+        #address-cells = <1>;
+        #size-cells = <1>;
+        ranges = <0x0 0xf0007000 0x40>;
+
+        kcs1: kcs1@0 {
+            compatible = "nuvoton,npcm750-kcs-bmc";
+            reg = <0x0 0x40>;
+            interrupts = <0 9 4>;
+            kcs_chan = <1>;
+            status = "disabled";
+        };
+
+        kcs2: kcs2@0 {
+            compatible = "nuvoton,npcm750-kcs-bmc";
+            reg = <0x0 0x40>;
+            interrupts = <0 9 4>;
+            kcs_chan = <2>;
+            status = "disabled";
+        };
+    };

Documentation/devicetree/bindings/mtd/npcm-spi.txt

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+* Nuvoton Serial Peripheral Interface(SPI)
+
+Required properties:
+  - compatible : "nuvoton,npcm750-spi" for NPCM750 BMC
+  - #address-cells : should be 1.
+  - #size-cells : should be 0.
+  - reg : the first contains the register location and length,
+          the second contains the memory mapping address and length
+  - reg-names: Should contain the reg names "control" and "memory"
+  - clocks : phandle of SPI reference clock.
+
+Optional properties:
+  - chip-max-address-map: Chip maximum address mapping for direct use.
+  			  the maximum address map size:
+			  NPCM7xx - 0x8000000 (128Mb)
+
+Example:
+
+spi0: spi@fb000000 {
+	compatible = "nuvoton,npcm750-spi";
+	#address-cells = <1>;
+	#size-cells = <0>;
+	reg = <0xfb000000 0x1000>, <0x80000000 0x10000000>;
+	reg-names = "control", "memory";
+	chip-max-address-map = <0x8000000>;
+	clocks = <&clk NPCM7XX_CLK_AHB>;
+	spi-nor@0 {
+			...
+	};
+};
+

Documentation/devicetree/bindings/net/nuvoton,npcm7xx-emc.txt

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+Nuvoton NPCM7XX 10/100 Ethernet MAC Controller (EMC)
+
+The NPCM750x provides two identical Ethernet MAC Controllers
+for WAN/LAN applications
+
+Required properties:
+- compatible      : "nuvoton,npcm750-emc" for Poleg NPCM750.
+- reg             : Offset and length of the register set for the device.
+- interrupts      : Contain the emc interrupts with flags for falling edge.
+					first interrupt dedicated to Txirq
+					second interrupt dedicated to Rxirq
+- clocks          : phandle of emc reference clock.
+- device_type	  : Should be "network"
+
+Example:
+
+emc0: eth@f0825000 {
+	device_type = "network";
+	compatible = "nuvoton,npcm750-emc";
+	reg = <0xf0825000 0x1000>;
+	interrupts = <0 16 4>, <0 15 4>;
+	clocks = <&clk NPCM7XX_CLK_EMC>;
+};
+