Modularised HLS(Vivado C/C++) based implementation of contrasting stencil applications targetting Xilinx FPGAs. The implementation currently includes the following applications.
poisson (5-point 2D stencil)
jac2D9pt (9-point 2D stencil)
jac3D7pt (7-point 3D stencil)
RTM (multiple stencil loops with 25-point 3D stencils)
blacksholes (3-point 1D stencil. Xilinx batch only)