Fix arm32 FIQ mask in IRQ/ABT/SVC/UND handlers for GICv3 #1748
Conversation
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
|
This takes care of the problem with unmasked foreign interrupts, but doesn't address the issue with masked local interrupts. In #1742 I've added an idea on how to address the latter problem. Since it's all related perhaps we'd better take care of both issues in the PR. |
|
@jenswi-linaro , good idea. I will do this. :) |
david-wang-2015
force-pushed
the
32bit-gicv3-fix
branch
from
345e2bb
to
64f8697
Compare
|
|
david-wang-2015
force-pushed
the
32bit-gicv3-fix
branch
from
64f8697
to
b21fceb
Compare
|
Rebased and refined. |
|
Please apply my r-b. |
added 2 commits
August 25, 2017 14:14
Disable native and foreign interrupts in thread handlers for arm32. The tee handlers can decide when the native interrupts can be enabled. Signed-off-by: David Wang <david.wang@arm.com> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
In Arm aarch32 mode, FIQ is not masked by hardware in IRQ mode. For GICv2, IRQ is for foreign interrupt and already masked by hardware in FIQ mode which is used for native interrupt. For GICv3, FIQ is for foreign interrupt. It's not masked by hardware in IRQ mode which is used for natvie interrupt. We need to mask it explicitly. Signed-off-by: David Wang <david.wang@arm.com> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
david-wang-2015
force-pushed
the
32bit-gicv3-fix
branch
from
b21fceb
to
52549f0
Compare
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
Add this suggestion to a batch that can be applied as a single commit.
This suggestion is invalid because no changes were made to the code.
Suggestions cannot be applied while the pull request is closed.
Suggestions cannot be applied while viewing a subset of changes.
Only one suggestion per line can be applied in a batch.
Add this suggestion to a batch that can be applied as a single commit.
Applying suggestions on deleted lines is not supported.
You must change the existing code in this line in order to create a valid suggestion.
Outdated suggestions cannot be applied.
This suggestion has been applied or marked resolved.
Suggestions cannot be applied from pending reviews.
Suggestions cannot be applied on multi-line comments.
Suggestions cannot be applied while the pull request is queued to merge.
Suggestion cannot be applied right now. Please check back later.
In Arm aarch32 mode, FIQ is not masked by hardware in IRQ, ABT, SVC and
UND mode.
For GICv2, IRQ is for foreign interrupt and already masked by hardware
in the exception modes listed above.
For GICv3, FIQ is for foreign interrupt. So, we need to mask FIQ
explicitly in these exception modes.
Signed-off-by: David Wang david.wang@arm.com