Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Jump to bottom

Fix arm32 FIQ mask in IRQ/ABT/SVC/UND handlers for GICv3 #1748

Merged
merged 2 commits into from
Aug 31, 2017
Merged

Fix arm32 FIQ mask in IRQ/ABT/SVC/UND handlers for GICv3 #1748

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
2 commits
Select commit Hold shift + click to select a range
cc1a3f8
Disable IRQ and FIQ in IRQ/ABT/SVC/UND thread handlers for arm32
Aug 9, 2017
52549f0
Fix FIQ mask for the native interrupt handler for arm32
Aug 24, 2017
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
34 changes: 34 additions & 0 deletions core/arch/arm/kernel/thread_a32.S
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -443,6 +443,16 @@ END_FUNC thread_rpc

/* The handler of native interrupt. */
.macro native_intr_handler mode:req
.ifc \mode\(),irq
/*
* Foreign interrupts should be masked.
* For GICv2, IRQ is for foreign interrupt and already masked by
* hardware in FIQ mode which is used for native interrupt.
* For GICv3, FIQ is for foreign interrupt. It's not masked by hardware
* in IRQ mode which is used for natvie interrupt.
*/
cpsid f
.endif
/*
* FIQ and IRQ have a +4 offset for lr compared to preferred return
* address
Expand Down Expand Up @@ -662,6 +672,12 @@ LOCAL_FUNC thread_abort_handler , :
thread_und_handler:
UNWIND( .fnstart)
UNWIND( .cantunwind)
/*
* Disable both foreign and native interrupts in the thread handlers.
* The tee handlers can decide when the native interrupts should
* be enabled.
*/
cpsid f /* IRQ is already masked by the hardware */
strd r0, r1, [sp, #THREAD_CORE_LOCAL_R0]
mrs r1, spsr
tst r1, #CPSR_T
Expand All @@ -671,12 +687,24 @@ UNWIND( .cantunwind)
b .thread_abort_generic

thread_dabort_handler:
/*
* Disable both foreign and native interrupts in the thread handlers.
* The tee handlers can decide when the native interrupts should
* be enabled.
*/
cpsid f /* IRQ is already masked by the hardware */
strd r0, r1, [sp, #THREAD_CORE_LOCAL_R0]
sub lr, lr, #8
mov r0, #ABORT_TYPE_DATA
b .thread_abort_generic

thread_pabort_handler:
/*
* Disable both foreign and native interrupts in the thread handlers.
* The tee handlers can decide when the native interrupts should
* be enabled.
*/
cpsid f /* IRQ is already masked by the hardware */
strd r0, r1, [sp, #THREAD_CORE_LOCAL_R0]
sub lr, lr, #4
mov r0, #ABORT_TYPE_PREFETCH
Expand Down Expand Up @@ -771,6 +799,12 @@ END_FUNC thread_abort_handler
LOCAL_FUNC thread_svc_handler , :
UNWIND( .fnstart)
UNWIND( .cantunwind)
/*
* Disable both foreign and native interrupts in the thread handlers.
* The tee handlers can decide when the native interrupts should
* be enabled.
*/
cpsid f /* IRQ is already masked by the hardware */
push {r0-r7, lr}
mrs r0, spsr
push {r0}
Expand Down
5 changes: 5 additions & 0 deletions core/arch/arm/tee/arch_svc.c
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -196,10 +196,15 @@ void __weak tee_svc_handler(struct thread_svc_regs *regs)
size_t scn;
size_t max_args;
syscall_t scf;
uint32_t state;

COMPILE_TIME_ASSERT(ARRAY_SIZE(tee_svc_syscall_table) ==
(TEE_SCN_MAX + 1));

/* Enable native interupts */
state = thread_get_exceptions();
thread_unmask_exceptions(state & ~THREAD_EXCP_NATIVE_INTR);

thread_user_save_vfp();

/* TA has just entered kernel mode */
Expand Down