Report all warnings as errors (#131)

OSCPU · Sep 14, 2023 · 5f07b3b · 5f07b3b
1 parent 165d06c
commit 5f07b3b
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Showing 44 changed files with 820 additions and 825 deletions.
diff --git a/build.sc b/build.sc
@@ -10,7 +10,8 @@ object ivys {
 trait CommonModule extends ScalaModule {
   override def scalaVersion = ivys.scala
 
-  override def scalacOptions = Seq("-Ymacro-annotations")
+  override def scalacOptions = Seq("-Ymacro-annotations") ++
+    Seq("-Xfatal-warnings", "-feature", "-deprecation", "-language:reflectiveCalls")
 }
 
 trait HasChisel3 extends ScalaModule {

diff --git a/difftest b/difftest
diff --git a/src/main/scala/bus/axi4/AXI4.scala b/src/main/scala/bus/axi4/AXI4.scala
@@ -122,10 +122,10 @@ class AXI4(val dataBits: Int = AXI4Parameters.dataBits, val idBits: Int = AXI4Pa
   override val r  = Flipped(Decoupled(new AXI4BundleR(dataBits, idBits)))
 
   def dump(name: String) = {
-    when (aw.fire()) { printf(p"${GTimer()},[${name}.aw] ${aw.bits}\n") }
-    when (w.fire()) { printf(p"${GTimer()},[${name}.w] ${w.bits}\n") }
-    when (b.fire()) { printf(p"${GTimer()},[${name}.b] ${b.bits}\n") }
-    when (ar.fire()) { printf(p"${GTimer()},[${name}.ar] ${ar.bits}\n") }
-    when (r.fire()) { printf(p"${GTimer()},[${name}.r] ${r.bits}\n") }
+    when (aw.fire) { printf(p"${GTimer()},[${name}.aw] ${aw.bits}\n") }
+    when (w.fire) { printf(p"${GTimer()},[${name}.w] ${w.bits}\n") }
+    when (b.fire) { printf(p"${GTimer()},[${name}.b] ${b.bits}\n") }
+    when (ar.fire) { printf(p"${GTimer()},[${name}.ar] ${ar.bits}\n") }
+    when (r.fire) { printf(p"${GTimer()},[${name}.r] ${r.bits}\n") }
   }
 }
diff --git a/src/main/scala/bus/simplebus/Crossbar.scala b/src/main/scala/bus/simplebus/Crossbar.scala
@@ -1,17 +1,17 @@
 /**************************************************************************************
 * Copyright (c) 2020 Institute of Computing Technology, CAS
 * Copyright (c) 2020 University of Chinese Academy of Sciences
-* 
+*
 * NutShell is licensed under Mulan PSL v2.
-* You can use this software according to the terms and conditions of the Mulan PSL v2. 
+* You can use this software according to the terms and conditions of the Mulan PSL v2.
 * You may obtain a copy of Mulan PSL v2 at:
-*             http://license.coscl.org.cn/MulanPSL2 
-* 
-* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER 
-* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY OR 
-* FIT FOR A PARTICULAR PURPOSE.  
+*             http://license.coscl.org.cn/MulanPSL2
+*
+* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY OR
+* FIT FOR A PARTICULAR PURPOSE.
 *
-* See the Mulan PSL v2 for more details.  
+* See the Mulan PSL v2 for more details.
 ***************************************************************************************/
 
 package bus.simplebus
@@ -36,9 +36,9 @@ class SimpleBusCrossbar1toN(addressSpace: List[(Long, Long)]) extends Module {
   val outMatchVec = VecInit(addressSpace.map(
     range => (addr >= range._1.U && addr < (range._1 + range._2).U)))
   val outSelVec = VecInit(PriorityEncoderOH(outMatchVec))
-  val outSelRespVec = RegEnable(next=outSelVec,
-                                init=VecInit(Seq.fill(outSelVec.length)(false.B)),
-                                enable=io.in.req.fire() && state === s_idle)
+  val outSelRespVec = RegEnable(outSelVec,
+                                VecInit(Seq.fill(outSelVec.length)(false.B)),
+                                io.in.req.fire && state === s_idle)
   val reqInvalidAddr = io.in.req.valid && !outSelVec.asUInt.orR
 
   when (reqInvalidAddr) {
@@ -50,11 +50,11 @@ class SimpleBusCrossbar1toN(addressSpace: List[(Long, Long)]) extends Module {
 
   switch (state) {
     is (s_idle) {
-      when (io.in.req.fire()) { state := s_resp }
+      when (io.in.req.fire) { state := s_resp }
       when (reqInvalidAddr) { state := s_error }
     }
-    is (s_resp) { when (io.in.resp.fire()) { state := s_idle } }
-    is (s_error) { when (io.in.resp.fire()) { state := s_idle } }
+    is (s_resp) { when (io.in.resp.fire) { state := s_idle } }
+    is (s_error) { when (io.in.resp.fire) { state := s_idle } }
   }
 
   // bind out.req channel
@@ -73,10 +73,10 @@ class SimpleBusCrossbar1toN(addressSpace: List[(Long, Long)]) extends Module {
   // io.in.resp.bits.exc.get := state === s_error
 
   Debug() {
-    when (io.in.req.fire()) {
+    when (io.in.req.fire) {
       printf(p"${GTimer()}: xbar: outSelVec = ${outSelVec}, outSel.req: ${io.in.req.bits}\n")
     }
-    when (io.in.resp.fire()) {
+    when (io.in.resp.fire) {
       printf(p"${GTimer()}: xbar: outSelVec = ${outSelVec}, outSel.resp: ${io.in.resp.bits}\n")
     }
   }
@@ -112,14 +112,14 @@ class SimpleBusCrossbarNto1(n: Int, userBits:Int = 0) extends Module {
 
   switch (state) {
     is (s_idle) {
-      when (thisReq.fire()) {
+      when (thisReq.fire) {
         inflightSrc := inputArb.io.chosen
         when (thisReq.bits.isRead()) { state := s_readResp }
         .elsewhen (thisReq.bits.isWriteLast() || thisReq.bits.isWriteSingle()) { state := s_writeResp }
       }
     }
-    is (s_readResp) { when (io.out.resp.fire() && io.out.resp.bits.isReadLast()) { state := s_idle } }
-    is (s_writeResp) { when (io.out.resp.fire()) { state := s_idle } }
+    is (s_readResp) { when (io.out.resp.fire && io.out.resp.bits.isReadLast) { state := s_idle } }
+    is (s_writeResp) { when (io.out.resp.fire) { state := s_idle } }
   }
 }
 
@@ -142,7 +142,7 @@ class SimpleBusAutoIDCrossbarNto1(n: Int, userBits: Int = 0) extends Module {
     val out = new SimpleBusUC(userBits, idBits = n)
   })
 
-  // Note: to use SimpleBusAutoIDCrossbarNto1, every master device must ensure resp.ready is always true 
+  // Note: to use SimpleBusAutoIDCrossbarNto1, every master device must ensure resp.ready is always true
 
   val reqValid = WireInit(VecInit(List.tabulate(n)(i => io.in(i).req.valid)))
   val reqSelect = PriorityEncoder(reqValid.asUInt)
@@ -160,7 +160,7 @@ class SimpleBusAutoIDCrossbarNto1(n: Int, userBits: Int = 0) extends Module {
   }
 
   io.out.req.valid := reqValid.asUInt.orR
-  io.out.req.bits.id.get := reqSelectVec.asUInt // Simple bus ID is OH 
+  io.out.req.bits.id.get := reqSelectVec.asUInt // Simple bus ID is OH
   io.out.resp.ready := true.B // io.in(reqSelect).resp.ready
   // assert(io.out.resp.ready)
 
@@ -175,10 +175,10 @@ class SimpleBusAutoIDCrossbarNto1(n: Int, userBits: Int = 0) extends Module {
   }
 
   Debug(){
-    when(io.out.req.fire()){
+    when(io.out.req.fire){
       printf("[Crossbar REQ] addr %x cmd %x select %b\n", io.out.req.bits.addr, io.out.req.bits.cmd, reqSelectVec)
     }
-    when(io.out.resp.fire()){
+    when(io.out.resp.fire){
       printf("[Crossbar RESP] data %x select %b\n", io.out.resp.bits.rdata, io.out.resp.bits.id.get)
     }
   }

diff --git a/src/main/scala/bus/simplebus/DistributedMem.scala b/src/main/scala/bus/simplebus/DistributedMem.scala
@@ -1,17 +1,17 @@
 /**************************************************************************************
 * Copyright (c) 2020 Institute of Computing Technology, CAS
 * Copyright (c) 2020 University of Chinese Academy of Sciences
-* 
+*
 * NutShell is licensed under Mulan PSL v2.
-* You can use this software according to the terms and conditions of the Mulan PSL v2. 
+* You can use this software according to the terms and conditions of the Mulan PSL v2.
 * You may obtain a copy of Mulan PSL v2 at:
-*             http://license.coscl.org.cn/MulanPSL2 
-* 
-* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER 
-* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY OR 
-* FIT FOR A PARTICULAR PURPOSE.  
+*             http://license.coscl.org.cn/MulanPSL2
+*
+* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY OR
+* FIT FOR A PARTICULAR PURPOSE.
 *
-* See the Mulan PSL v2 for more details.  
+* See the Mulan PSL v2 for more details.
 ***************************************************************************************/
 
 package bus.simplebus
@@ -29,14 +29,14 @@ class DistributedMem(memByte: Int, dualPort: Boolean, delayCycles: Int = 0, data
     val ro = Flipped(new SimpleBusUC)
   })
 
-  val wordNum = memByte / 8 
+  val wordNum = memByte / 8
   val nBank = XLEN / 8
   val memAddrBits = log2Up(wordNum)
   def Index(addr: UInt): UInt = addr(memAddrBits + 2 - 1, 2)
 
   val rwIdx = Index(io.rw.req.bits.addr)
   val roIdx = Index(io.ro.req.bits.addr)
-  val wen = io.rw.isWrite()
+  val wen = io.rw.isWrite
   val wdataVec = VecInit.tabulate(nBank) { i => io.rw.req.bits.wdata(8 * (i + 1) - 1, 8 * i) }
   val wmask = VecInit.tabulate(nBank) { i => io.rw.req.bits.wmask(i).asBool }
 
@@ -56,16 +56,16 @@ class DistributedMem(memByte: Int, dualPort: Boolean, delayCycles: Int = 0, data
     val state = RegInit(s_idle)
     switch (state) {
       is (s_idle) {
-        when (p.req.fire()) { state := Mux(p.resp.fire(), s_idle, s_reading) }
+        when (p.req.fire) { state := Mux(p.resp.fire, s_idle, s_reading) }
       }
       is (s_reading) {
-        when (p.resp.fire()) { state := s_idle }
+        when (p.resp.fire) { state := s_idle }
       }
     }
 
     p.req.ready := state === s_idle
     p.resp.bits.rdata := rdata
-    p.resp.valid := (if (delayCycles == 0) p.req.fire() else Counter(state === s_reading, delayCycles)._2)
+    p.resp.valid := (if (delayCycles == 0) p.req.fire else Counter(state === s_reading, delayCycles)._2)
   }
 
   readPort(io.rw, rwData)

diff --git a/src/main/scala/bus/simplebus/SimpleBus.scala b/src/main/scala/bus/simplebus/SimpleBus.scala
@@ -1,17 +1,17 @@
 /**************************************************************************************
 * Copyright (c) 2020 Institute of Computing Technology, CAS
 * Copyright (c) 2020 University of Chinese Academy of Sciences
-* 
+*
 * NutShell is licensed under Mulan PSL v2.
-* You can use this software according to the terms and conditions of the Mulan PSL v2. 
+* You can use this software according to the terms and conditions of the Mulan PSL v2.
 * You may obtain a copy of Mulan PSL v2 at:
-*             http://license.coscl.org.cn/MulanPSL2 
-* 
-* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER 
-* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY OR 
-* FIT FOR A PARTICULAR PURPOSE.  
+*             http://license.coscl.org.cn/MulanPSL2
+*
+* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY OR
+* FIT FOR A PARTICULAR PURPOSE.
 *
-* See the Mulan PSL v2 for more details.  
+* See the Mulan PSL v2 for more details.
 ***************************************************************************************/
 
 package bus.simplebus
@@ -60,7 +60,7 @@ class SimpleBusReqBundle(val userBits: Int = 0, val addrBits: Int = 32, val idBi
     p"wmask = 0x${Hexadecimal(wmask)}, wdata = 0x${Hexadecimal(wdata)}"
   }
 
-  def apply(addr: UInt, cmd: UInt, size: UInt, wdata: UInt, wmask: UInt, user: UInt = 0.U, id: UInt = 0.U) {
+  def apply(addr: UInt, cmd: UInt, size: UInt, wdata: UInt, wmask: UInt, user: UInt = 0.U, id: UInt = 0.U) = {
     this.addr := addr
     this.cmd := cmd
     this.size := size
@@ -88,27 +88,27 @@ class SimpleBusRespBundle(val userBits: Int = 0, val idBits: Int = 0) extends Si
 
   override def toPrintable: Printable = p"rdata = ${Hexadecimal(rdata)}, cmd = ${cmd}"
 
-  def isReadLast() = cmd === SimpleBusCmd.readLast
-  def isProbeHit() = cmd === SimpleBusCmd.probeHit
-  def isProbeMiss() = cmd === SimpleBusCmd.probeMiss
-  def isWriteResp() = cmd === SimpleBusCmd.writeResp
-  def isPrefetch() = cmd === SimpleBusCmd.prefetch
+  def isReadLast = cmd === SimpleBusCmd.readLast
+  def isProbeHit = cmd === SimpleBusCmd.probeHit
+  def isProbeMiss = cmd === SimpleBusCmd.probeMiss
+  def isWriteResp = cmd === SimpleBusCmd.writeResp
+  def isPrefetch = cmd === SimpleBusCmd.prefetch
 }
 
 // Uncache
 class SimpleBusUC(val userBits: Int = 0, val addrBits: Int = 32, val idBits: Int = 0) extends SimpleBusBundle {
   val req = Decoupled(new SimpleBusReqBundle(userBits, addrBits, idBits))
   val resp = Flipped(Decoupled(new SimpleBusRespBundle(userBits, idBits)))
 
-  def isWrite() = req.valid && req.bits.isWrite()
-  def isRead()  = req.valid && req.bits.isRead()
-  def toAXI4Lite() = SimpleBus2AXI4Converter(this, new AXI4Lite, false)
+  def isWrite = req.valid && req.bits.isWrite()
+  def isRead  = req.valid && req.bits.isRead()
+  def toAXI4Lite = SimpleBus2AXI4Converter(this, new AXI4Lite, false)
   def toAXI4(isFromCache: Boolean = false) = SimpleBus2AXI4Converter(this, new AXI4, isFromCache)
-  def toMemPort() = SimpleBus2MemPortConverter(this, new MemPortIo(32))
+  def toMemPort = SimpleBus2MemPortConverter(this, new MemPortIo(32))
 
   def dump(name: String) = {
-    when (req.fire()) { printf(p"${GTimer()},[${name}] ${req.bits}\n") }
-    when (resp.fire()) { printf(p"${GTimer()},[${name}] ${resp.bits}\n") }
+    when (req.fire) { printf(p"${GTimer()},[${name}] ${req.bits}\n") }
+    when (resp.fire) { printf(p"${GTimer()},[${name}] ${resp.bits}\n") }
   }
 }
 
@@ -121,10 +121,10 @@ class SimpleBusUCExpender(val userBits: Int, val userVal: UInt, val addrBits: In
   io.out.req.valid := io.in.req.valid
   io.in.req.ready := io.out.req.ready
   io.out.req.bits.addr := io.in.req.bits.addr
-  io.out.req.bits.size := io.in.req.bits.size 
-  io.out.req.bits.cmd := io.in.req.bits.cmd 
-  io.out.req.bits.wmask := io.in.req.bits.wmask 
-  io.out.req.bits.wdata := io.in.req.bits.wdata 
+  io.out.req.bits.size := io.in.req.bits.size
+  io.out.req.bits.cmd := io.in.req.bits.cmd
+  io.out.req.bits.wmask := io.in.req.bits.wmask
+  io.out.req.bits.wdata := io.in.req.bits.wdata
   io.out.req.bits.user.get := userVal
   io.in.resp.valid := io.out.resp.valid
   io.out.resp.ready := io.in.resp.ready

diff --git a/src/main/scala/bus/simplebus/ToAXI4.scala b/src/main/scala/bus/simplebus/ToAXI4.scala
@@ -1,17 +1,17 @@
 /**************************************************************************************
 * Copyright (c) 2020 Institute of Computing Technology, CAS
 * Copyright (c) 2020 University of Chinese Academy of Sciences
-* 
+*
 * NutShell is licensed under Mulan PSL v2.
-* You can use this software according to the terms and conditions of the Mulan PSL v2. 
+* You can use this software according to the terms and conditions of the Mulan PSL v2.
 * You may obtain a copy of Mulan PSL v2 at:
-*             http://license.coscl.org.cn/MulanPSL2 
-* 
-* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER 
-* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY OR 
-* FIT FOR A PARTICULAR PURPOSE.  
+*             http://license.coscl.org.cn/MulanPSL2
+*
+* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY OR
+* FIT FOR A PARTICULAR PURPOSE.
 *
-* See the Mulan PSL v2 for more details.  
+* See the Mulan PSL v2 for more details.
 ***************************************************************************************/
 
 package bus.simplebus
@@ -102,7 +102,7 @@ class AXI42SimpleBusConverter() extends Module {
     }
   }
 
-  when (isState(axi_write) && axi.w.fire()) {
+  when (isState(axi_write) && axi.w.fire) {
     mem.req.valid := true.B
     req.cmd := Mux(aw_reg.len === 0.U, SimpleBusCmd.write,
       Mux(w.last, SimpleBusCmd.writeLast, SimpleBusCmd.writeBurst))
@@ -134,11 +134,11 @@ class AXI42SimpleBusConverter() extends Module {
   axi.b.valid := bresp_en && mem.resp.valid
   axi.b.bits.resp := AXI4Parameters.RESP_OKAY
 
-  when (axi.ar.fire()) { assert(mem.req.fire() && !isInflight()); }
-  when (axi.aw.fire()) { assert(!isInflight()); }
-  when (axi.w.fire()) { assert(mem.req .fire() && isState(axi_write)); }
-  when (axi.b.fire()) { assert(mem.resp.fire() && isState(axi_write)); }
-  when (axi.r.fire()) { assert(mem.resp.fire() && isState(axi_read)); }
+  when (axi.ar.fire) { assert(mem.req.fire && !isInflight()); }
+  when (axi.aw.fire) { assert(!isInflight()); }
+  when (axi.w.fire) { assert(mem.req .fire && isState(axi_write)); }
+  when (axi.b.fire) { assert(mem.resp.fire && isState(axi_write)); }
+  when (axi.r.fire) { assert(mem.resp.fire && isState(axi_read)); }
 }
 
 
@@ -184,14 +184,14 @@ class SimpleBus2AXI4Converter[OT <: AXI4Lite](outType: OT, isFromCache: Boolean)
   mem.resp.bits.cmd  := Mux(rlast, SimpleBusCmd.readLast, 0.U)
 
   val wSend = Wire(Bool())
-  val awAck = BoolStopWatch(axi.aw.fire(), wSend)
-  val wAck = BoolStopWatch(axi.w.fire() && wlast, wSend)
-  wSend := (axi.aw.fire() && axi.w.fire() && wlast) || (awAck && wAck)
-  val wen = RegEnable(mem.req.bits.isWrite(), mem.req.fire())
-
-  axi.ar.valid := mem.isRead()
-  axi.aw.valid := mem.isWrite() && !awAck
-  axi.w .valid := mem.isWrite() && !wAck
+  val awAck = BoolStopWatch(axi.aw.fire, wSend)
+  val wAck = BoolStopWatch(axi.w.fire && wlast, wSend)
+  wSend := (axi.aw.fire && axi.w.fire && wlast) || (awAck && wAck)
+  val wen = RegEnable(mem.req.bits.isWrite(), mem.req.fire)
+
+  axi.ar.valid := mem.isRead
+  axi.aw.valid := mem.isWrite && !awAck
+  axi.w .valid := mem.isWrite && !wAck
   mem.req.ready  := Mux(mem.req.bits.isWrite(), !wAck && axi.w.ready, axi.ar.ready)
 
   axi.r.ready  := mem.resp.ready

diff --git a/src/main/scala/device/AXI4CLINT.scala b/src/main/scala/device/AXI4CLINT.scala
@@ -61,7 +61,7 @@ class AXI4CLINT(sim: Boolean = false) extends AXI4SlaveModule(new AXI4Lite, new
   def getOffset(addr: UInt) = addr(15,0)
 
   RegMap.generate(mapping, getOffset(raddr), in.r.bits.data,
-    getOffset(waddr), in.w.fire(), in.w.bits.data, MaskExpand(in.w.bits.strb))
+    getOffset(waddr), in.w.fire, in.w.bits.data, MaskExpand(in.w.bits.strb))
 
   io.extra.get.mtip := RegNext(mtime >= mtimecmp)
   io.extra.get.msip := RegNext(msip =/= 0.U)