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CSR: initialize mepc to zero (#122)
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The least significant bit of mepc should be zero. This is a temp
fix to co-simulate ready-to-run/microbench.bin with Spike.
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poemonsense authored Sep 10, 2023
1 parent 84d8ee2 commit 71eb376
Showing 1 changed file with 1 addition and 1 deletion.
2 changes: 1 addition & 1 deletion src/main/scala/nutcore/backend/fu/CSR.scala
Original file line number Diff line number Diff line change
Expand Up @@ -253,7 +253,7 @@ class CSR(implicit val p: NutCoreConfig) extends NutCoreModule with HasCSRConst{
val mcounteren = RegInit(UInt(XLEN.W), 0.U)
val mcause = RegInit(UInt(XLEN.W), 0.U)
val mtval = RegInit(UInt(XLEN.W), 0.U)
val mepc = Reg(UInt(XLEN.W))
val mepc = RegInit(UInt(XLEN.W), 0.U)

val mie = RegInit(0.U(XLEN.W))
val mipWire = WireInit(0.U.asTypeOf(new Interrupt))
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