Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Jump to bottom

Optimize LatencyPipe code with Chisel3 style #133

Merged
merged 1 commit into from
Sep 17, 2023
Merged

Optimize LatencyPipe code with Chisel3 style #133

Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
13 changes: 7 additions & 6 deletions src/main/scala/utils/LatencyPipe.scala
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -2,13 +2,14 @@

package utils

import Chisel._
import chisel3._
import chisel3.util._

class LatencyPipe[T <: Data](typ: T, latency: Int) extends Module {
val io = new Bundle {
val in = Decoupled(typ).flip
val out = Decoupled(typ)
}
val io = IO(new Bundle {
val in = Flipped(DecoupledIO(typ))
val out = DecoupledIO(typ)
})

def doN[T](n: Int, func: T => T, in: T): T =
(0 until n).foldLeft(in)((last, _) => func(last))
Expand All @@ -18,7 +19,7 @@ class LatencyPipe[T <: Data](typ: T, latency: Int) extends Module {

object LatencyPipe {
def apply[T <: Data](in: DecoupledIO[T], latency: Int): DecoupledIO[T] = {
val pipe = Module(new LatencyPipe(in.bits, latency))
val pipe = Module(new LatencyPipe(in.bits.cloneType, latency))
pipe.io.in <> in
pipe.io.out
}
Expand Down
Loading