Fix typo for privileged

src/main/scala/bus/axi4/AXI4.scala

@@ -29,7 +29,7 @@ object AXI4Parameters extends HasNutCoreParameter {
   def CACHE_MODIFIABLE = 2.U(cacheBits.W)
   def CACHE_BUFFERABLE = 1.U(cacheBits.W)
 
-  def PROT_PRIVILEDGED = 1.U(protBits.W)
+  def PROT_PRIVILEGED = 1.U(protBits.W)
   def PROT_INSECURE    = 2.U(protBits.W)
   def PROT_INSTRUCTION = 4.U(protBits.W)
 

src/main/scala/bus/simplebus/ToAXI4.scala

@@ -156,7 +156,7 @@ class SimpleBus2AXI4Converter[OT <: AXI4Lite](outType: OT, isFromCache: Boolean)
   val (ar, aw, w, r, b) = (axi.ar.bits, axi.aw.bits, axi.w.bits, axi.r.bits, axi.b.bits)
 
   ar.addr  := mem.req.bits.addr
-  ar.prot  := AXI4Parameters.PROT_PRIVILEDGED
+  ar.prot  := AXI4Parameters.PROT_PRIVILEGED
   w.data := mem.req.bits.wdata
   w.strb := mem.req.bits.wmask
 

src/main/scala/device/AXI4DMA.scala

@@ -70,7 +70,7 @@ class AXI4DMA extends AXI4SlaveModule(new AXI4Lite, new DMABundle) {
     state := Mux(len <= step.U, s_idle, s_read_req)
   }
 
-  dma.ar.bits.prot := AXI4Parameters.PROT_PRIVILEDGED
+  dma.ar.bits.prot := AXI4Parameters.PROT_PRIVILEGED
   dma.ar.bits.id := 0.U
   dma.ar.bits.size := log2Ceil(step).U
   dma.ar.bits.burst := AXI4Parameters.BURST_INCR

src/main/scala/nutcore/Bundle.scala

@@ -1,17 +1,17 @@
 /**************************************************************************************
 * Copyright (c) 2020 Institute of Computing Technology, CAS
 * Copyright (c) 2020 University of Chinese Academy of Sciences
-* 
+*
 * NutShell is licensed under Mulan PSL v2.
-* You can use this software according to the terms and conditions of the Mulan PSL v2. 
+* You can use this software according to the terms and conditions of the Mulan PSL v2.
 * You may obtain a copy of Mulan PSL v2 at:
-*             http://license.coscl.org.cn/MulanPSL2 
-* 
-* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER 
-* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY OR 
-* FIT FOR A PARTICULAR PURPOSE.  
+*             http://license.coscl.org.cn/MulanPSL2
+*
+* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY OR
+* FIT FOR A PARTICULAR PURPOSE.
 *
-* See the Mulan PSL v2 for more details.  
+* See the Mulan PSL v2 for more details.
 ***************************************************************************************/
 
 package nutcore
@@ -120,14 +120,14 @@ class MMUIO extends NutCoreBundle {
   // val valid = Output(Bool())
   // val isStore = Output(Bool())
 
-  val priviledgeMode = Input(UInt(2.W))
+  val privilegeMode = Input(UInt(2.W))
   val status_sum = Input(Bool())
   val status_mxr = Input(Bool())
 
   val loadPF = Output(Bool())
   val storePF = Output(Bool())
-  val addr = Output(UInt(VAddrBits.W)) 
-  
+  val addr = Output(UInt(VAddrBits.W))
+
   def isPF() = loadPF || storePF
 }
 
@@ -153,7 +153,7 @@ class TLBExuIO extends NutCoreBundle {
 }
 
 class InstFetchIO extends NutCoreBundle {
-  val pc = Output(UInt(VAddrBits.W)) // real PC will be regenerated in IBF 
+  val pc = Output(UInt(VAddrBits.W)) // real PC will be regenerated in IBF
   val pnpc = Output(UInt(VAddrBits.W))
   val brIdx = Output(UInt(4.W))
   val instValid = Output(UInt(4.W))

src/main/scala/nutcore/Decode.scala

@@ -75,7 +75,7 @@ object Instructions extends HasInstrType with HasNutCoreParameter {
   def DecodeTable = RVIInstr.table ++ NutCoreTrap.table ++
     (if (HasMExtension) RVMInstr.table else Array.empty) ++
     (if (HasCExtension) RVCInstr.table else Array.empty) ++
-    Priviledged.table ++
+    Privileged.table ++
     RVAInstr.table ++
     RVZicsrInstr.table ++ RVZifenceiInstr.table
 }

src/main/scala/nutcore/backend/fu/CSR.scala

@@ -365,8 +365,8 @@ class CSR(implicit val p: NutCoreConfig) extends NutCoreModule with HasCSRConst{
     lrAddr := setLrAddr
   }
 
-  // Hart Priviledge Mode
-  val priviledgeMode = RegInit(UInt(2.W), ModeM)
+  // Hart Privilege Mode
+  val privilegeMode = RegInit(UInt(2.W), ModeM)
 
   // perfcnt
   val hasPerfCnt = EnablePerfCnt && !p.FPGAPlatform
@@ -471,7 +471,7 @@ class CSR(implicit val p: NutCoreConfig) extends NutCoreModule with HasCSRConst{
 
   // General CSR wen check
   val wen = (valid && func =/= CSROpType.jmp) && (addr =/= Satp.U || satpLegalMode) && !io.isBackendException
-  val isIllegalMode  = priviledgeMode < addr(9, 8)
+  val isIllegalMode  = privilegeMode < addr(9, 8)
   val justRead = (func === CSROpType.set || func === CSROpType.seti) && src1 === 0.U  // csrrs and csrrsi are exceptions when their src1 is zero
   val isIllegalWrite = wen && (addr(11, 10) === "b11".U) && !justRead  // Write a read-only CSR register
   val isIllegalAccess = isIllegalMode || isIllegalWrite
@@ -498,12 +498,12 @@ class CSR(implicit val p: NutCoreConfig) extends NutCoreModule with HasCSRConst{
   val isUret = addr === privUret   && func === CSROpType.jmp && !io.isBackendException
 
   Debug(wen, "csr write: pc %x addr %x rdata %x wdata %x func %x\n", io.cfIn.pc, addr, rdata, wdata, func)
-  Debug(wen, "[MST] time %d pc %x mstatus %x mideleg %x medeleg %x mode %x\n", GTimer(), io.cfIn.pc, mstatus, mideleg , medeleg, priviledgeMode)
+  Debug(wen, "[MST] time %d pc %x mstatus %x mideleg %x medeleg %x mode %x\n", GTimer(), io.cfIn.pc, mstatus, mideleg , medeleg, privilegeMode)
 
   // MMU Permission Check
 
-  // def MMUPermissionCheck(ptev: Bool, pteu: Bool): Bool = ptev && !(priviledgeMode === ModeU && !pteu) && !(priviledgeMode === ModeS && pteu && mstatusStruct.sum.asBool)
-  // def MMUPermissionCheckLoad(ptev: Bool, pteu: Bool): Bool = ptev && !(priviledgeMode === ModeU && !pteu) && !(priviledgeMode === ModeS && pteu && mstatusStruct.sum.asBool) && (pter || (mstatusStruct.mxr && ptex))
+  // def MMUPermissionCheck(ptev: Bool, pteu: Bool): Bool = ptev && !(privilegeMode === ModeU && !pteu) && !(privilegeMode === ModeS && pteu && mstatusStruct.sum.asBool)
+  // def MMUPermissionCheckLoad(ptev: Bool, pteu: Bool): Bool = ptev && !(privilegeMode === ModeU && !pteu) && !(privilegeMode === ModeS && pteu && mstatusStruct.sum.asBool) && (pter || (mstatusStruct.mxr && ptex))
   // imem
   // val imemPtev = true.B
   // val imemPteu = true.B
@@ -525,9 +525,9 @@ class CSR(implicit val p: NutCoreConfig) extends NutCoreModule with HasCSRConst{
   // assert(!hasLoadPageFault)
   // assert(!hasStorePageFault)
 
-  //TODO: Havn't test if io.dmemMMU.priviledgeMode is correct yet
-  io.imemMMU.priviledgeMode := priviledgeMode
-  io.dmemMMU.priviledgeMode := Mux(mstatusStruct.mprv.asBool, mstatusStruct.mpp, priviledgeMode)
+  //TODO: Havn't test if io.dmemMMU.privilegeMode is correct yet
+  io.imemMMU.privilegeMode := privilegeMode
+  io.dmemMMU.privilegeMode := Mux(mstatusStruct.mprv.asBool, mstatusStruct.mpp, privilegeMode)
   io.imemMMU.status_sum := mstatusStruct.sum.asBool
   io.dmemMMU.status_sum := mstatusStruct.sum.asBool
   io.imemMMU.status_mxr := DontCare
@@ -563,18 +563,18 @@ class CSR(implicit val p: NutCoreConfig) extends NutCoreModule with HasCSRConst{
 
   when(hasInstrPageFault || hasLoadPageFault || hasStorePageFault){
     val tval = Mux(hasInstrPageFault, Mux(io.cfIn.crossPageIPFFix, SignExt((io.cfIn.pc + 2.U)(VAddrBits-1,0), XLEN), SignExt(io.cfIn.pc(VAddrBits-1,0), XLEN)), SignExt(dmemPagefaultAddr, XLEN))
-    when(priviledgeMode === ModeM){
+    when(privilegeMode === ModeM){
       mtval := tval
     }.otherwise{
       stval := tval
     }
-    Debug("[PF] %d: ipf %b tval %x := addr %x pc %x priviledgeMode %x\n", GTimer(), hasInstrPageFault, tval, SignExt(dmemPagefaultAddr, XLEN), io.cfIn.pc, priviledgeMode)
+    Debug("[PF] %d: ipf %b tval %x := addr %x pc %x privilegeMode %x\n", GTimer(), hasInstrPageFault, tval, SignExt(dmemPagefaultAddr, XLEN), io.cfIn.pc, privilegeMode)
   }
 
   when(hasLoadAddrMisaligned || hasStoreAddrMisaligned)
   {
     mtval := SignExt(dmemAddrMisalignedAddr, XLEN)
-    Debug("[ML] %d: addr %x pc %x priviledgeMode %x\n", GTimer(), SignExt(dmemAddrMisalignedAddr, XLEN), io.cfIn.pc, priviledgeMode)
+    Debug("[ML] %d: addr %x pc %x privilegeMode %x\n", GTimer(), SignExt(dmemAddrMisalignedAddr, XLEN), io.cfIn.pc, privilegeMode)
   }
 
   // Exception and Intr
@@ -598,11 +598,11 @@ class CSR(implicit val p: NutCoreConfig) extends NutCoreModule with HasCSRConst{
   mipRaiseIntr.e.s := mip.e.s | seip
 
   val ideleg =  (mideleg & mipRaiseIntr.asUInt)
-  def priviledgedEnableDetect(x: Bool): Bool = Mux(x, ((priviledgeMode === ModeS) && mstatusStruct.ie.s) || (priviledgeMode < ModeS),
-                                   ((priviledgeMode === ModeM) && mstatusStruct.ie.m) || (priviledgeMode < ModeM))
+  def privilegedEnableDetect(x: Bool): Bool = Mux(x, ((privilegeMode === ModeS) && mstatusStruct.ie.s) || (privilegeMode < ModeS),
+                                   ((privilegeMode === ModeM) && mstatusStruct.ie.m) || (privilegeMode < ModeM))
 
   val intrVecEnable = Wire(Vec(12, Bool()))
-  intrVecEnable.zip(ideleg.asBools).map{case(x,y) => x := priviledgedEnableDetect(y)}
+  intrVecEnable.zip(ideleg.asBools).map{case(x,y) => x := privilegedEnableDetect(y)}
   val intrVec = mie(11,0) & mipRaiseIntr.asUInt & intrVecEnable.asUInt
   BoringUtils.addSource(WireInit(intrVec), "intrVecIDU")
   // val intrNO = PriorityEncoder(intrVec)
@@ -617,10 +617,10 @@ class CSR(implicit val p: NutCoreConfig) extends NutCoreModule with HasCSRConst{
   val csrExceptionVec = Wire(Vec(16, Bool()))
   csrExceptionVec.map(_ := false.B)
   csrExceptionVec(breakPoint) := io.in.valid && isEbreak
-  csrExceptionVec(ecallM) := priviledgeMode === ModeM && io.in.valid && isEcall
-  csrExceptionVec(ecallS) := priviledgeMode === ModeS && io.in.valid && isEcall
-  csrExceptionVec(ecallU) := priviledgeMode === ModeU && io.in.valid && isEcall
-  csrExceptionVec(illegalInstr) := (isIllegalAddr || isIllegalAccess) && wen && !io.isBackendException // Trigger an illegal instr exception when unimplemented csr is being read/written or not having enough priviledge
+  csrExceptionVec(ecallM) := privilegeMode === ModeM && io.in.valid && isEcall
+  csrExceptionVec(ecallS) := privilegeMode === ModeS && io.in.valid && isEcall
+  csrExceptionVec(ecallU) := privilegeMode === ModeU && io.in.valid && isEcall
+  csrExceptionVec(illegalInstr) := (isIllegalAddr || isIllegalAccess) && wen && !io.isBackendException // Trigger an illegal instr exception when unimplemented csr is being read/written or not having enough privilege
   csrExceptionVec(loadPageFault) := hasLoadPageFault
   csrExceptionVec(storePageFault) := hasStorePageFault
   val iduExceptionVec = io.cfIn.exceptionVec
@@ -641,15 +641,15 @@ class CSR(implicit val p: NutCoreConfig) extends NutCoreModule with HasCSRConst{
 
   Debug(raiseExceptionIntr, "excin %b excgen %b", csrExceptionVec.asUInt, iduExceptionVec.asUInt)
   Debug(raiseExceptionIntr, "int/exc: pc %x int (%d):%x exc: (%d):%x\n",io.cfIn.pc, intrNO, io.cfIn.intrVec.asUInt, exceptionNO, raiseExceptionVec.asUInt)
-  Debug(raiseExceptionIntr, "[MST] time %d pc %x mstatus %x mideleg %x medeleg %x mode %x\n", GTimer(), io.cfIn.pc, mstatus, mideleg , medeleg, priviledgeMode)
+  Debug(raiseExceptionIntr, "[MST] time %d pc %x mstatus %x mideleg %x medeleg %x mode %x\n", GTimer(), io.cfIn.pc, mstatus, mideleg , medeleg, privilegeMode)
   Debug(io.redirect.valid, "redirect to %x\n", io.redirect.target)
   Debug(resetSatp, "satp reset\n")
 
   // Branch control
 
   val deleg = Mux(raiseIntr, mideleg , medeleg)
-  // val delegS = ((deleg & (1 << (causeNO & 0xf))) != 0) && (priviledgeMode < ModeM);
-  val delegS = (deleg(causeNO(3,0))) && (priviledgeMode < ModeM)
+  // val delegS = ((deleg & (1 << (causeNO & 0xf))) != 0) && (privilegeMode < ModeM);
+  val delegS = (deleg(causeNO(3,0))) && (privilegeMode < ModeM)
   val tvalWen = !(hasInstrPageFault || hasLoadPageFault || hasStorePageFault || hasLoadAddrMisaligned || hasStoreAddrMisaligned) || raiseIntr // in nutcore-riscv64, no exception will come together with PF
 
   ret := isMret || isSret || isUret
@@ -663,7 +663,7 @@ class CSR(implicit val p: NutCoreConfig) extends NutCoreModule with HasCSRConst{
     val mstatusNew = WireInit(mstatus.asTypeOf(new MstatusStruct))
     // mstatusNew.mpp.m := ModeU //TODO: add mode U
     mstatusNew.ie.m := mstatusOld.pie.m
-    priviledgeMode := mstatusOld.mpp
+    privilegeMode := mstatusOld.mpp
     mstatusNew.pie.m := true.B
     mstatusNew.mpp := ModeU
     mstatus := mstatusNew.asUInt
@@ -676,7 +676,7 @@ class CSR(implicit val p: NutCoreConfig) extends NutCoreModule with HasCSRConst{
     val mstatusNew = WireInit(mstatus.asTypeOf(new MstatusStruct))
     // mstatusNew.mpp.m := ModeU //TODO: add mode U
     mstatusNew.ie.s := mstatusOld.pie.s
-    priviledgeMode := Cat(0.U(1.W), mstatusOld.spp)
+    privilegeMode := Cat(0.U(1.W), mstatusOld.spp)
     mstatusNew.pie.s := true.B
     mstatusNew.spp := ModeU
     mstatus := mstatusNew.asUInt
@@ -689,7 +689,7 @@ class CSR(implicit val p: NutCoreConfig) extends NutCoreModule with HasCSRConst{
     val mstatusNew = WireInit(mstatus.asTypeOf(new MstatusStruct))
     // mstatusNew.mpp.m := ModeU //TODO: add mode U
     mstatusNew.ie.u := mstatusOld.pie.u
-    priviledgeMode := ModeU
+    privilegeMode := ModeU
     mstatusNew.pie.u := true.B
     mstatus := mstatusNew.asUInt
     retTarget := uepc(VAddrBits-1, 0)
@@ -702,24 +702,24 @@ class CSR(implicit val p: NutCoreConfig) extends NutCoreModule with HasCSRConst{
     when (delegS) {
       scause := causeNO
       sepc := SignExt(io.cfIn.pc, XLEN)
-      mstatusNew.spp := priviledgeMode
+      mstatusNew.spp := privilegeMode
       mstatusNew.pie.s := mstatusOld.ie.s
       mstatusNew.ie.s := false.B
-      priviledgeMode := ModeS
+      privilegeMode := ModeS
       when(tvalWen){stval := 0.U} // TODO: should not use =/=
       // printf("[*] mstatusNew.spp %x\n", mstatusNew.spp)
       // trapTarget := stvec(VAddrBits-1. 0)
     }.otherwise {
       mcause := causeNO
       mepc := SignExt(io.cfIn.pc, XLEN)
-      mstatusNew.mpp := priviledgeMode
+      mstatusNew.mpp := privilegeMode
       mstatusNew.pie.m := mstatusOld.ie.m
       mstatusNew.ie.m := false.B
-      priviledgeMode := ModeM
+      privilegeMode := ModeM
       when(tvalWen){mtval := 0.U} // TODO: should not use =/=
       // trapTarget := mtvec(VAddrBits-1. 0)
     }
-    // mstatusNew.pie.m := LookupTree(priviledgeMode, List(
+    // mstatusNew.pie.m := LookupTree(privilegeMode, List(
     //   ModeM -> mstatusOld.ie.m,
     //   ModeH -> mstatusOld.ie.h, //ERROR
     //   ModeS -> mstatusOld.ie.s,
@@ -911,7 +911,7 @@ class CSR(implicit val p: NutCoreConfig) extends NutCoreModule with HasCSRConst{
     diffWrapper := DontCare
 
     val difftest = diffWrapper.csrState
-    difftest.priviledgeMode := priviledgeMode
+    difftest.privilegeMode := privilegeMode
     difftest.mstatus := mstatus
     difftest.sstatus := mstatus & sstatusRmask
     difftest.mepc := mepc

src/main/scala/nutcore/frontend/IDU.scala

@@ -184,7 +184,7 @@ class Decoder(implicit val p: NutCoreConfig) extends NutCoreModule with HasInstr
   }
 
   io.out.bits.ctrl.isNutCoreTrap := (instr === NutCoreTrap.TRAP) && io.in.valid
-  io.isWFI := (instr === Priviledged.WFI) && io.in.valid
+  io.isWFI := (instr === Privileged.WFI) && io.in.valid
   io.isBranch := VecInit(RV32I_BRUInstr.table.map(i => i._2.tail(1) === fuOpType).toIndexedSeq).asUInt.orR &&
     fuType === FuType.bru
 

src/main/scala/nutcore/isa/Priviledged.scala → src/main/scala/nutcore/isa/Privileged.scala

@@ -1,17 +1,17 @@
 /**************************************************************************************
 * Copyright (c) 2020 Institute of Computing Technology, CAS
 * Copyright (c) 2020 University of Chinese Academy of Sciences
-* 
+*
 * NutShell is licensed under Mulan PSL v2.
-* You can use this software according to the terms and conditions of the Mulan PSL v2. 
+* You can use this software according to the terms and conditions of the Mulan PSL v2.
 * You may obtain a copy of Mulan PSL v2 at:
-*             http://license.coscl.org.cn/MulanPSL2 
-* 
-* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER 
-* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY OR 
-* FIT FOR A PARTICULAR PURPOSE.  
+*             http://license.coscl.org.cn/MulanPSL2
+*
+* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY OR
+* FIT FOR A PARTICULAR PURPOSE.
 *
-* See the Mulan PSL v2 for more details.  
+* See the Mulan PSL v2 for more details.
 ***************************************************************************************/
 
 package nutcore
@@ -21,14 +21,14 @@ import chisel3.util._
 
 import top.Settings
 
-object Priviledged extends HasInstrType {
+object Privileged extends HasInstrType {
   def ECALL   = BitPat("b000000000000_00000_000_00000_1110011")
   def EBREAK  = BitPat("b000000000001_00000_000_00000_1110011")
   def MRET    = BitPat("b001100000010_00000_000_00000_1110011")
   def SRET    = BitPat("b000100000010_00000_000_00000_1110011")
   def SFANCE_VMA = BitPat("b0001001_?????_?????_000_00000_1110011")
   def FENCE   = BitPat("b????????????_?????_000_?????_0001111")
-  def WFI     = BitPat("b0001000_00101_00000_000_00000_1110011") 
+  def WFI     = BitPat("b0001000_00101_00000_000_00000_1110011")
 
   val table_s = Array(
     SRET           -> List(InstrI, FuType.csr, CSROpType.jmp),