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Add Versal SOC family support #237
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#endif /* defined(versal) */ | ||
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#define MB (1024 * 1024UL) | ||
#define GB (1024 * 1024 * 1024UL) |
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Seems that thes definitions are used in several files... could be moved to utilities.h, the update of the other files can be done later
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ok will move this. thank you
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@arnopo updated copyrights |
also moved the MB/GB part to utilities.h |
collect (PROJECT_LIB_HEADERS sys.h) | ||
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add_subdirectory(../xlnx_common ${CMAKE_CURRENT_BINARY_DIR}/../xlnx_common) | ||
# vim: expandtab:ts=2:sw=2:smartindent |
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to remove vim
line ( and you can also remove some other instances)
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updated
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vim line still present
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Hi @arnopo are there any pending changes? |
@@ -1,6 +1,4 @@ | |||
collect (PROJECT_LIB_HEADERS sys.h) | |||
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collect (PROJECT_LIB_SOURCES sys.c) | |||
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add_subdirectory(../xlnx_common ${CMAKE_CURRENT_BINARY_DIR}/../xlnx_common) | |||
# vim: expandtab:ts=2:sw=2:smartindent |
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also one occurrence here
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resolved @arnopo
collect (PROJECT_LIB_HEADERS sys.h) | ||
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add_subdirectory(../xlnx_common ${CMAKE_CURRENT_BINARY_DIR}/../xlnx_common) | ||
# vim: expandtab:ts=2:sw=2:smartindent |
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vim line still present
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removed the vim line in new commits |
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running checkpatch, I just saw a check to fix. With that LGTM
#include "xreg_cortexa53.h" | ||
#endif /* defined(versal) */ | ||
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./scripts/checkpatch.pl --strict --codespell 237.patch
237.patch:87: CHECK:LINE_SPACING: Please don't use multiple blank lines
#87: FILE: lib/system/generic/xlnx_common/zynqmp_aarch64/sys.c:28:
+
+
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Sorry! thanks @arnopo i ran checkpatch and the only remaining lines are due to Xilinx-BSP functions now (same as it was). latest commits reflect the fix. thanks
Enable cache, IPI, exception and shared-memory operations on Versal A72 for Libmetal. Additionally, as the code for A72 and A53 is almost identical, move the common code to generic/xlnx_common/zynqmp_aarch64 and differentiate the slight differences with macro checks. Signed-off-by: Ben Levinsky <ben.levinsky@xilinx.com> Acked-by: tanmay.shah@xilinx.com
Enable cache, IPI, exception and shared-memory operations on Versal A78 for Libmetal. Signed-off-by: Ben Levinsky <ben.levinsky@amd.com>
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Looks good to go now.
Add support for Versal and Versal_Net SoCs APU cores A72 and A78