OpenCAPI
Ecosystem for developers using OpenCAPI, a new high performance coherent bus interface
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ThymesisFlow
ThymesisFlow PublicMemory Disaggregation on POWER9 with OpenCAPI 3.0 M1 & C1
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omi_device_ice
omi_device_ice PublicAn example OMI Device FPGA with 2 DDR4 memory ports
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OpenCAPI3.0_Client_RefDesign
OpenCAPI3.0_Client_RefDesign PublicAn example OpenCAPI 3.0 FPGA reference design for accelerator endpoint development
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- OpenCAPI3.0_Client_RefDesign Public
An example OpenCAPI 3.0 FPGA reference design for accelerator endpoint development
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