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[AArch64] Fixing a SPI interrupt ID miscalculation #1156

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Merged
kuqin12 merged 4 commits into from
Dec 4, 2025
Merged

[AArch64] Fixing a SPI interrupt ID miscalculation #1156

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a207a2f
fix spi counting
kuqin12 Dec 4, 2025
e6b2f73
do not need to disable interrupts as this is done in the setup
kuqin12 Dec 4, 2025
93858c6
Merge branch 'main' into fix_spi
kuqin12 Dec 4, 2025
fe32459
Merge branch 'main' into fix_spi
kuqin12 Dec 4, 2025
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11 changes: 1 addition & 10 deletions core/patina_internal_cpu/src/interrupts/aarch64/gic_manager.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -157,15 +157,6 @@ impl AArch64InterruptInitializer {
let mut gic_v3 = unsafe { GicV3::new(gicd, gicr, r_count, true) };
gic_v3.setup(cpu_r_idx);

// Disable all interrupts and set priority to 0x80.
gic_v3.enable_all_interrupts(false);
for i in IntId::private() {
gic_v3.set_interrupt_priority(i, Some(cpu_r_idx), 0x80).map_err(|_| EfiError::DeviceError)?;
}
for spi in 0..gic_v3.typer().num_spis() {
gic_v3.set_interrupt_priority(IntId::spi(spi), None, 0x80).map_err(|_| EfiError::DeviceError)?;
}

// Set binary point reg to 0x7 (no preemption)
// Safety: this is a legal value for BPR1 register.
// Refer to "Arm Generic Interrupt Controller Architecture Specification GIC
Expand All @@ -184,7 +175,7 @@ impl AArch64InterruptInitializer {
x if x < IntId::SGI_COUNT => IntId::sgi(x),
x if x < IntId::SGI_COUNT + IntId::PPI_COUNT => IntId::ppi(x - IntId::SGI_COUNT),
x => {
let int_id = IntId::spi(x - IntId::SGI_COUNT + IntId::PPI_COUNT);
let int_id = IntId::spi(x - IntId::SGI_COUNT - IntId::PPI_COUNT);
if self.gic_v3.typer().num_spis() < int_id.into() {
Err(EfiError::InvalidParameter)?;
}
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