drm/i915/psr: Nuke PSR support for VLV and CHV

PSR hardware and hence the driver code for VLV and CHV deviates a lot from
their DDI counterparts. While the feature has been disabled for a long time
now, retaining support for these platforms is a maintenance burden. There
have been multiple refactoring commits to just keep the existing code for
these platforms in line with the rest. There are known issues that need to
be fixed to enable PSR on these platforms, and there is no PSR capable
platform in CI to ensure the code does not break again if we get around to
fixing the existing issues. On account of all these reasons, let's nuke
this code for now and bring it back if a need arises in the future.

Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Acked-by: Jani Nikula <jani.nikula@intel.com>
Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180511230059.19387-1-dhinakaran.pandiyan@intel.com

drivers/gpu/drm/i915/i915_debugfs.c

@@ -2643,8 +2643,6 @@ static int i915_edp_psr_status(struct seq_file *m, void *data)
 {
  struct drm_i915_private *dev_priv = node_to_i915(m->private);
  u32 psrperf = 0;
- u32 stat[3];
- enum pipe pipe;
  bool enabled = false;
  bool sink_support;
 
@@ -2665,47 +2663,17 @@ static int i915_edp_psr_status(struct seq_file *m, void *data)
  seq_printf(m, "Re-enable work scheduled: %s\n",
  yesno(work_busy(&dev_priv->psr.work.work)));
 
- if (HAS_DDI(dev_priv)) {
- if (dev_priv->psr.psr2_enabled)
- enabled = I915_READ(EDP_PSR2_CTL) & EDP_PSR2_ENABLE;
- else
- enabled = I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE;
- } else {
- for_each_pipe(dev_priv, pipe) {
- enum transcoder cpu_transcoder =
- intel_pipe_to_cpu_transcoder(dev_priv, pipe);
- enum intel_display_power_domain power_domain;
-
- power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
- if (!intel_display_power_get_if_enabled(dev_priv,
- power_domain))
- continue;
-
- stat[pipe] = I915_READ(VLV_PSRSTAT(pipe)) &
- VLV_EDP_PSR_CURR_STATE_MASK;
- if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
- (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
- enabled = true;
-
- intel_display_power_put(dev_priv, power_domain);
- }
- }
+ if (dev_priv->psr.psr2_enabled)
+ enabled = I915_READ(EDP_PSR2_CTL) & EDP_PSR2_ENABLE;
+ else
+ enabled = I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE;
 
  seq_printf(m, "Main link in standby mode: %s\n",
  yesno(dev_priv->psr.link_standby));
 
- seq_printf(m, "HW Enabled & Active bit: %s", yesno(enabled));
-
- if (!HAS_DDI(dev_priv))
- for_each_pipe(dev_priv, pipe) {
- if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
- (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
- seq_printf(m, " pipe %c", pipe_name(pipe));
- }
- seq_puts(m, "\n");
+ seq_printf(m, "HW Enabled & Active bit: %s\n", yesno(enabled));
 
  /*
- * VLV/CHV PSR has no kind of performance counter
  * SKL+ Perf counter is reset to 0 everytime DC state is entered
  */
  if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {

drivers/gpu/drm/i915/i915_drv.h

@@ -607,7 +607,6 @@ struct i915_psr {
  bool link_standby;
  bool colorimetry_support;
  bool alpm;
- bool has_hw_tracking;
  bool psr2_enabled;
  u8 sink_sync_latency;
  bool debug;

drivers/gpu/drm/i915/i915_pci.c

@@ -340,7 +340,6 @@ static const struct intel_device_info intel_valleyview_info = {
  GEN(7),
  .is_lp = 1,
  .num_pipes = 2,
- .has_psr = 1,
  .has_runtime_pm = 1,
  .has_rc6 = 1,
  .has_gmch_display = 1,
@@ -433,7 +432,6 @@ static const struct intel_device_info intel_cherryview_info = {
  .is_lp = 1,
  .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
  .has_64bit_reloc = 1,
- .has_psr = 1,
  .has_runtime_pm = 1,
  .has_resource_streamer = 1,
  .has_rc6 = 1,

drivers/gpu/drm/i915/intel_drv.h

@@ -1917,8 +1917,6 @@ void intel_psr_flush(struct drm_i915_private *dev_priv,
  unsigned frontbuffer_bits,
  enum fb_op_origin origin);
 void intel_psr_init(struct drm_i915_private *dev_priv);
-void intel_psr_single_frame_update(struct drm_i915_private *dev_priv,
- unsigned frontbuffer_bits);
 void intel_psr_compute_config(struct intel_dp *intel_dp,
  struct intel_crtc_state *crtc_state);
 void intel_psr_irq_control(struct drm_i915_private *dev_priv, bool debug);

drivers/gpu/drm/i915/intel_frontbuffer.c

@@ -153,8 +153,6 @@ void intel_frontbuffer_flip_prepare(struct drm_i915_private *dev_priv,
  /* Remove stale busy bits due to the old buffer. */
  dev_priv->fb_tracking.busy_bits &= ~frontbuffer_bits;
  spin_unlock(&dev_priv->fb_tracking.lock);
-
- intel_psr_single_frame_update(dev_priv, frontbuffer_bits);
 }
 
 /**