fix(tval): update cpu.instr when set-jmp

* move cpu.instr update to set-jmp * always open RVC exception check
OpenXiangShan · Oct 24, 2024 · 11bbaf1 · 11bbaf1
1 parent 20d0ef1
commit 11bbaf1
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Showing 2 changed files with 1 addition and 14 deletions.
diff --git a/src/cpu/cpu-exec.c b/src/cpu/cpu-exec.c
@@ -556,9 +556,6 @@ static int execute(int n) {
     fetch_decode(&s, cpu.pc);
     cpu.debug.current_pc = s.pc;
     cpu.pc = s.snpc;
-#ifdef CONFIG_TVAL_EX_II
-    cpu.instr = s.isa.instr.val;
-#endif
 #ifdef CONFIG_SHARE
     if (unlikely(dynamic_config.debug_difftest)) {
       fprintf(stderr, "(%d) [NEMU] pc = 0x%lx inst %x\n", getpid(), s.pc,
@@ -615,9 +612,6 @@ void fetch_decode(Decode *s, vaddr_t pc) {
 static void update_global() {
   update_instr_cnt();
   cpu.pc = prev_s->pc;
-  #ifdef CONFIG_TVAL_EX_II
-    cpu.instr = prev_s->isa.instr.val;
-  #endif // CONFIG_TVAL_EX_II
 }
 #endif
 
@@ -649,6 +643,7 @@ void cpu_exec(uint64_t n) {
   PUSH_CONTEXT(&cause);
   if (cause) {
     n_remain -= prev_s->idx_in_bb - 1;
+    cpu.instr = IFDEF(CONFIG_TVAL_EX_II, prev_s->isa.instr.val);
     // Here is exception handle
 #ifdef CONFIG_PERF_OPT
     update_global();

diff --git a/src/isa/riscv64/instr/rvc/decode.h b/src/isa/riscv64/instr/rvc/decode.h
@@ -94,14 +94,10 @@ static inline def_DHelper(C_ADDI16SP) {
   uint32_t instr = s->isa.instr.val;
   sword_t simm = (SEXT(BITS(instr, 12, 12), 1) << 9) | (BITS(instr, 4, 3) << 7) |
     (BITS(instr, 5, 5) << 6) | (BITS(instr, 2, 2) << 5) | (BITS(instr, 6, 6) << 4);
-#ifdef CONFIG_SHARE
   // C.ADDI16SP is only valid when nzimm!=0; the code point with nzimm=0 is reserved.
   if (unlikely(simm == 0)) {
     longjmp_exception(EX_II);
   }
-#else
-  assert(simm != 0);
-#endif // CONFIG_SHARE
   decode_op_i(s, id_src2, simm, false);
   decode_op_r(s, id_dest, 2, false);
 }
@@ -116,12 +112,10 @@ static inline void decode_C_LxSP(Decode *s, int rotate, bool is_fp) {
   uint32_t imm6 = (BITS(s->isa.instr.val, 12, 12) << 5) | BITS(s->isa.instr.val, 6, 2);
   decode_C_xxSP(s, imm6, rotate);
   uint32_t rd = BITS(s->isa.instr.val, 11, 7);
-#ifdef CONFIG_SHARE
   // C.LxSP is only valid when rd!=x0; the code points with rd=x0 are reserved.
   if (unlikely(rd == 0 && !is_fp)) {
     longjmp_exception(EX_II);
   }
-#endif // CONFIG_SHARE
   if (is_fp) {
 #ifdef CONFIG_FPU_NONE
     longjmp_exception(EX_II);
@@ -323,12 +317,10 @@ static inline void decode_C_rs1_rs2_rd(Decode *s, bool is_rs1_zero, bool is_rs2_
 }
 
 static inline def_DHelper(C_JR) {
-  #ifdef CONFIG_SHARE
   // C.JR is only valid when rs1!=x0; the code point with rs1=x0 is reserved.
   if (unlikely(BITS(s->isa.instr.val, 11, 7) == 0)) {
     longjmp_exception(EX_II);
   }
-#endif // CONFIG_SHARE
   decode_op_r(s, id_src1, BITS(s->isa.instr.val, 11, 7), true);
 }