rv64,isa: change CSR orders to align with difftest

OpenXiangShan · Sep 8, 2023 · 452757f · 452757f
1 parent 3f9a7e1
commit 452757f
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Showing 2 changed files with 13 additions and 7 deletions.
diff --git a/ready-to-run b/ready-to-run
diff --git a/src/isa/riscv64/include/isa-def.h b/src/isa/riscv64/include/isa-def.h
@@ -70,20 +70,26 @@ typedef struct {
 #endif // CONFIG_FPU_NONE
 
   // shadow CSRs for difftest
-  uint64_t pc;
-  uint64_t mstatus, mcause, mepc;
-  uint64_t sstatus, scause, sepc;
-
-  uint64_t satp, mip, mie, mscratch, sscratch, mideleg, medeleg;
-  uint64_t mtval, stval, mtvec, stvec;
   uint64_t mode;
+  uint64_t mstatus, sstatus;
+  uint64_t mepc, sepc;
+  uint64_t mtval, stval;
+  uint64_t mtvec, stvec;
+  uint64_t mcause, scause;
+  uint64_t satp;
+  uint64_t mip, mie;
+  uint64_t mscratch, sscratch;
+  uint64_t mideleg, medeleg;
+  uint64_t pc;
   // Above will be synced by regcpy when run difftest, DO NOT TOUCH
+
 #ifdef CONFIG_RVH
   uint64_t v; // virtualization mode
   uint64_t mtval2, mtinst, hstatus, hideleg, hedeleg;
   uint64_t hcounteren, htval, htinst, hgatp, vsstatus;
   uint64_t vstvec, vsepc, vscause, vstval, vsatp, vsscratch;
 #endif
+
 #ifdef CONFIG_RVV
   //vector
   union {