Wrap FPU code in CONFIG_FPU_NONE

OpenXiangShan · Sep 7, 2023 · 7faa957 · 7faa957
1 parent de77981
commit 7faa957
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Showing 8 changed files with 56 additions and 23 deletions.
diff --git a/lib-include/difftest.h b/lib-include/difftest.h
@@ -31,23 +31,26 @@ enum { DIFFTEST_TO_DUT, DIFFTEST_TO_REF };
 #elif defined(__ISA_riscv32__)
 # define DIFFTEST_REG_SIZE (sizeof(uint32_t) * 33) // GRPs + pc
 #elif defined(__ISA_riscv64__)
-
-#if defined RV64_FULL_DIFF
+#ifdef RV64_FULL_DIFF
+#ifdef CONFIG_FPU_NONE
+#define BASE_SIZE (sizeof(uint64_t) * (32 + 1 + 6 + 11 + 1))
+#else
 #define BASE_SIZE (sizeof(uint64_t) * (32 + 32 + 1 + 6 + 11 + 1))
+#endif
 // GRPs + FPRs + pc + [m|s][status|cause|epc] + other necessary CSRs + mode
 #else
 #define BASE_SIZE (sizeof(uint64_t) * (32 + 1)) // GRPs + pc
 #endif //RV64_FULL_DIFF
 
 #if defined (RV64_FULL_DIFF) && defined (CONFIG_RVV)
 #define RVV_EXT_REG_SIZE (sizeof(uint64_t) * (64 + 7))
-#else 
+#else
 #define RVV_EXT_REG_SIZE 0
 #endif //CONFIG_RVV
 
 #if defined (RV64_FULL_DIFF) && defined (CONFIG_RVH)
-#define RVH_EXT_REG_SIZE (sizeof(uint64_t) * (1 + 16)) // v-mode + HCSRS 
-#else 
+#define RVH_EXT_REG_SIZE (sizeof(uint64_t) * (1 + 16)) // v-mode + HCSRS
+#else
 #define RVH_EXT_REG_SIZE 0
 #endif //CONFIG_RVH
 

diff --git a/src/checkpoint/serializer.cpp b/src/checkpoint/serializer.cpp
@@ -130,7 +130,7 @@ void Serializer::serializeRegs() {
       IntRegStartAddr, IntRegStartAddr + 32 * 8
       );
 
-
+#ifndef CONFIG_FPU_NONE
   auto *floatRegCpt = (uint64_t *) (get_pmem() + FloatRegStartAddr);
   for (unsigned i = 0; i < 32; i++) {
     *(floatRegCpt + i) = cpu.fpr[i]._64;
@@ -139,7 +139,7 @@ void Serializer::serializeRegs() {
       FLOAT_REG_CPT_ADDR, FLOAT_REG_CPT_ADDR + 32 * 8,
       FloatRegStartAddr, FloatRegStartAddr + 32 * 8
       );
-
+#endif // CONFIG_FPU_NONE
 
   auto *pc = (uint64_t *) (get_pmem() + PCAddr);
   *pc = cpu.pc;

diff --git a/src/isa/riscv64/difftest/ref.c b/src/isa/riscv64/difftest/ref.c
@@ -35,11 +35,11 @@ void ramcmp() {
   }
 }
 
-// csr_prepare() & csr_writeback() are used to maintain 
+// csr_prepare() & csr_writeback() are used to maintain
 // a compact mirror of critical CSRs
-// For processor difftest only 
+// For processor difftest only
 #ifdef CONFIG_RVH
-#define MIDELEG_FORCED_MASK ((1 << 12) | (1 << 10) | (1 << 6) | (1 << 2)) 
+#define MIDELEG_FORCED_MASK ((1 << 12) | (1 << 10) | (1 << 6) | (1 << 2))
 #endif //CONFIG_RVH
 
 #ifdef CONFIG_RVV_010
@@ -126,21 +126,21 @@ void csr_writeback() {
   vlenb->val   = cpu.vlenb;
 #endif //CONFIG_RVV
 #ifdef CONFIG_RVH
-  mtval2->val  = cpu.mtval2; 
-  mtinst->val  = cpu.mtinst; 
+  mtval2->val  = cpu.mtval2;
+  mtinst->val  = cpu.mtinst;
   hstatus->val = cpu.hstatus;
   hideleg->val = cpu.hideleg;
   hedeleg->val = cpu.hedeleg;
   hcounteren->val = cpu.hcounteren;
-  htval->val   = cpu.htval;  
+  htval->val   = cpu.htval;
   htinst->val  = cpu.htinst;
-  hgatp->val   = cpu.hgatp;   
+  hgatp->val   = cpu.hgatp;
   vsstatus->val= cpu.vsstatus;
   vstvec->val  = cpu.vstvec;
-  vsepc->val   = cpu.vsepc; 
+  vsepc->val   = cpu.vsepc;
   vscause->val = cpu.vscause;
   vstval->val  = cpu.vstval;
-  vsatp->val   = cpu.vsatp;  
+  vsatp->val   = cpu.vsatp;
   vsscratch->val = cpu.vsscratch;
 #endif
 }
@@ -269,7 +269,7 @@ void isa_difftest_raise_intr(word_t NO) {
   stable_log_begin = restore_count;
   spec_log_begin = restore_count + AHEAD_LENGTH;
   cpu_exec(AHEAD_LENGTH);
-  
+
   lightqs_take_spec_reg_snapshot();
   // clint_take_spec_snapshot();
 #endif // CONFIG_LIGHTQS
@@ -331,7 +331,7 @@ void isa_difftest_query_ref(void *result_buffer, uint64_t type) {
       cpu.query_mem_event.pc = cpu.debug.current_pc; // update pc
       size = sizeof(cpu.query_mem_event);
       memcpy(result_buffer, &cpu.query_mem_event, size);
-      // nemu result buffer will be flushed after query 
+      // nemu result buffer will be flushed after query
       // printf_with_pid("mem_access %x\n", cpu.query_mem_event.mem_access);
       // printf_with_pid("mem_access_is_load %x\n", cpu.query_mem_event.mem_access_is_load);
       // printf_with_pid("mem_access_vaddr %lx\n", cpu.query_mem_event.mem_access_vaddr);
@@ -382,9 +382,11 @@ void dump_regs() {
   for (int i = 0; i < 32; i++) {
     fprintf(fp, "gpr %d %lx\n", i, cpu.gpr[i]._64);
   }
+#ifndef CONFIG_FPU_NONE
   for (int i = 0; i < 32; i++) {
     fprintf(fp, "fpr %d %lx\n", i, cpu.fpr[i]._64);
   }
+#endif // CONFIG_FPU_NONE
 }
 
 #ifdef CONFIG_MULTICORE_DIFF

diff --git a/src/isa/riscv64/include/isa-def.h b/src/isa/riscv64/include/isa-def.h
@@ -63,9 +63,11 @@ typedef struct {
     uint64_t _64;
   } gpr[32];
 
+#ifndef CONFIG_FPU_NONE
   union {
     uint64_t _64;
   } fpr[32];
+#endif // CONFIG_FPU_NONE
 
   // shadow CSRs for difftest
   uint64_t pc;

diff --git a/src/isa/riscv64/include/isa-exec.h b/src/isa/riscv64/include/isa-exec.h
@@ -18,8 +18,10 @@
 #include "../instr/rvi/exec.h"
 #include "../instr/rvc/exec.h"
 #include "../instr/rvm/exec.h"
+#ifndef CONFIG_FPU_NONE
 #include "../instr/rvf/exec.h"
 #include "../instr/rvd/exec.h"
+#endif // CONFIG_FPU_NONE
 #include "../instr/rva/exec.h"
 #include "../instr/priv/exec.h"
 #ifdef CONFIG_RVB

diff --git a/src/isa/riscv64/instr/decode.c b/src/isa/riscv64/instr/decode.c
@@ -35,14 +35,18 @@ static inline uint32_t get_instr(Decode *s) {
   void concat(decode_op_, name) (Decode *s, Operand *op, word_t val, bool flag)
 
 #include "rvi/decode.h"
+#ifndef CONFIG_FPU_NONE
 #include "rvf/decode.h"
+#endif // CONFIG_FPU_NONE
 #include "rvm/decode.h"
 #include "rva/decode.h"
 #include "rvc/decode.h"
-#include "rvd/decode.h"
 #include "priv/decode.h"
+#ifndef CONFIG_FPU_NONE
+#include "rvd/decode.h"
+#endif // CONFIG_FPU_NONE
 #ifdef CONFIG_RVV
-  #include "rvv/decode.h"
+#include "rvv/decode.h"
 #endif // CONFIG_RVV
 
 def_THelper(main) {

diff --git a/src/isa/riscv64/instr/rvc/decode.h b/src/isa/riscv64/instr/rvc/decode.h
@@ -122,7 +122,13 @@ static inline void decode_C_LxSP(Decode *s, int rotate, bool is_fp) {
     longjmp_exception(EX_II);
   }
 #endif // CONFIG_SHARE
-  if (is_fp) decode_op_fr(s, id_dest, rd, false);
+  if (is_fp) {
+#ifdef CONFIG_FPU_NONE
+    longjmp_exception(EX_II);
+#else
+    decode_op_fr(s, id_dest, rd, false);
+#endif // CONFIG_FPU_NONE
+  }
   else decode_op_r(s, id_dest, rd, false);
 }
 
@@ -144,7 +150,13 @@ static inline void decode_C_SxSP(Decode *s, int rotate, bool is_fp) {
   uint32_t imm6 = BITS(s->isa.instr.val, 12, 7);
   decode_C_xxSP(s, imm6, rotate);
   uint32_t rs2 = BITS(s->isa.instr.val, 6, 2);
-  if (is_fp) decode_op_fr(s, id_dest, rs2, true);
+  if (is_fp) {
+#ifdef CONFIG_FPU_NONE
+    longjmp_exception(EX_II);
+#else
+    decode_op_fr(s, id_dest, rs2, true);
+#endif // CONFIG_FPU_NONE
+  }
   else decode_op_r(s, id_dest, rs2, true);
 }
 
@@ -181,7 +193,13 @@ static inline void decode_C_ldst_common(Decode *s, int rotate, bool is_store, bo
   uint32_t imm5 = (BITS(instr, 12, 10) << 2) | BITS(instr, 6, 5);
   uint32_t imm = ror_imm(imm5, 5, rotate) << 1;
   decode_op_i(s, id_src2, imm, false);
-  if (is_fp) decode_op_fr(s, id_dest, creg2reg(BITS(instr, 4, 2)), is_store);
+  if (is_fp) {
+#ifdef CONFIG_FPU_NONE
+    longjmp_exception(EX_II);
+#else
+    decode_op_fr(s, id_dest, creg2reg(BITS(instr, 4, 2)), is_store);
+#endif // CONFIG_FPU_NONE
+  }
   else decode_op_r(s, id_dest, creg2reg(BITS(instr, 4, 2)), is_store);
 }
 

diff --git a/src/isa/riscv64/reg.c b/src/isa/riscv64/reg.c
@@ -43,12 +43,14 @@ void isa_reg_display() {
       printf("\n");
     }
   }
+#ifndef CONFIG_FPU_NONE
   for (i = 0; i < 32; i ++) {
     printf("%4s: " FMT_WORD " ", fpregsl[i], cpu.fpr[i]._64);
     if (i % 4 == 3) {
       printf("\n");
     }
   }
+#endif // CONFIG_FPU_NONE
   printf("pc: " FMT_WORD " mstatus: " FMT_WORD " mcause: " FMT_WORD " mepc: " FMT_WORD "\n",
       cpu.pc, mstatus->val, mcause->val, mepc->val);
   printf("%22s sstatus: " FMT_WORD " scause: " FMT_WORD " sepc: " FMT_WORD "\n",