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RV64: fix several bugs of H extention and performance optimization #133

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merged 4 commits into from
Jul 28, 2023
Merged

RV64: fix several bugs of H extention and performance optimization #133

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86e8dbe
fix: compile error when enable NEMU debug
cebarobot Jul 27, 2023
a66167f
fix: ebreak problem when enable Performance optimization
cebarobot Jul 27, 2023
265f58f
fix: flush tcache when changing virtualization mode
cebarobot Jul 28, 2023
80d4a08
fix: remove redundant code
cebarobot Jul 28, 2023
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6 changes: 0 additions & 6 deletions src/isa/riscv64/include/isa-all-instr.h
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Original file line number Diff line number Diff line change
Expand Up @@ -33,12 +33,6 @@
#define AMO_INSTR_TERNARY(f) f(atomic)
#endif

#ifdef CONFIG_RV_DEBUG
#define RV_D_NULLARY(f) f(ebreak)
#else
#define RV_D_NULLARY(f)
#endif

#ifdef CONFIG_RVH
#ifdef CONFIG_RV_SVINVAL
#define RVH_INST_BINARY(f) f(hfence_vvma) f(hfence_gvma) f(hinval_vvma) f(hinval_gvma) \
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13 changes: 7 additions & 6 deletions src/isa/riscv64/instr/decode.c
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Expand Up @@ -20,7 +20,7 @@
#include <cpu/cpu.h>
#include <cpu/ifetch.h>
#include <cpu/decode.h>
#include <isa-all-instr.h>
#include "../include/isa-all-instr.h"


def_all_THelper();
Expand Down Expand Up @@ -130,25 +130,26 @@ int isa_fetch_decode(Decode *s) {
s->jnpc = id_dest->imm; s->type = INSTR_TYPE_B; break;

case EXEC_ID_p_ret: case EXEC_ID_c_jr: case EXEC_ID_c_jalr: case EXEC_ID_jalr:
IFDEF(CONFIG_DEBUG, case EXEC_ID_mret: case EXEC_ID_sret: case EXEC_ID_ecall:)
IFDEF(CONFIG_DEBUG, case EXEC_ID_mret: case EXEC_ID_sret: case EXEC_ID_ecall: case EXEC_ID_ebreak:)
s->type = INSTR_TYPE_I; break;

#ifndef CONFIG_DEBUG
#ifdef CONFIG_RVH
case EXEC_ID_priv:
#else
#else // CONFIG_RVH
case EXEC_ID_system:
#endif
#endif // CONFIG_RVH
if (s->isa.instr.i.funct3 == 0) {
switch (s->isa.instr.csr.csr) {
case 0: // ecall
case 0x0: // ecall
case 0x1: // ebreak
case 0x102: // sret
case 0x302: // mret
s->type = INSTR_TYPE_I;
}
}
break;
#endif
#endif // CONFIG_DEBUG
}

return idx;
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3 changes: 0 additions & 3 deletions src/isa/riscv64/instr/priv/exec.h
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Expand Up @@ -23,9 +23,6 @@ def_EHelper(name) { \
}

#ifdef CONFIG_DEBUG
#ifdef CONFIG_RV_DEBUG
def_SYS_EHelper(ebreak)
#endif

#ifdef CONFIG_RVH
#define def_hld_template(name) \
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4 changes: 3 additions & 1 deletion src/isa/riscv64/system/intr.c
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Expand Up @@ -15,6 +15,7 @@
***************************************************************************************/

#include <cpu/difftest.h>
#include <cpu/cpu.h>
#include "../local-include/csr.h"
#include "../local-include/intr.h"

Expand Down Expand Up @@ -129,6 +130,7 @@ word_t raise_intr(word_t NO, vaddr_t epc) {
hstatus->spvp = cpu.mode;
}
cpu.v = 0;
set_sys_state_flag(SYS_STATE_FLUSH_TCACHE);
#else
if (delegS) {
#endif
Expand Down Expand Up @@ -162,7 +164,7 @@ word_t raise_intr(word_t NO, vaddr_t epc) {
mstatus->gva = (NO == EX_IGPF || NO == EX_LGPF || NO == EX_SGPF ||
((v || hld_st_temp) && ((0 <= NO && NO <= 7 && NO != 2) || NO == EX_IPF || NO == EX_LPF || NO == EX_SPF)));
mstatus->mpv = cpu.v;
cpu.v = 0;
cpu.v = 0;set_sys_state_flag(SYS_STATE_FLUSH_TCACHE);
#endif
mcause->val = NO;
mepc->val = epc;
Expand Down
2 changes: 2 additions & 0 deletions src/isa/riscv64/system/priv.c
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Expand Up @@ -640,6 +640,7 @@ static word_t priv_instr(uint32_t op, const rtlreg_t *src) {
if (cpu.v == 0){
cpu.v = hstatus->spv;
hstatus->spv = 0;
set_sys_state_flag(SYS_STATE_FLUSH_TCACHE);
}else if (cpu.v == 1){
if((cpu.mode == MODE_S && hstatus->vtsr) || cpu.mode < MODE_S){
longjmp_exception(EX_VI);
Expand Down Expand Up @@ -684,6 +685,7 @@ static word_t priv_instr(uint32_t op, const rtlreg_t *src) {
#ifdef CONFIG_RVH
cpu.v = mstatus->mpv;
mstatus->mpv = 0;
set_sys_state_flag(SYS_STATE_FLUSH_TCACHE);
#endif // CONFIG_RVH
if (mstatus->mpp != MODE_M) { mstatus->mprv = 0; }
mstatus->mpp = MODE_U;
Expand Down
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