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difftest,dut: support RISC-V vector extension #184

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merged 12 commits into from
Sep 22, 2023
Merged

difftest,dut: support RISC-V vector extension #184

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1a60df2
FIX: difftest/dut.c macro definition modification
weidingliu Sep 18, 2023
e2343f5
add vector extension difftest
weidingliu Sep 18, 2023
b3d9889
some api
weidingliu Sep 19, 2023
828ed09
vsstatus have bug
weidingliu Sep 20, 2023
2cf8c09
Add vector extension difftest dut
weidingliu Sep 21, 2023
7770ab1
difftest dut: Add suport for RISCV vector extension difftest with spike
weidingliu Sep 21, 2023
1d018d6
difftest dut: Add suport for RISCV vector extension difftest with spike
weidingliu Sep 21, 2023
88768a6
difftest dut: Add suport for RISCV vector extension difftest with spike
weidingliu Sep 21, 2023
6cad31a
difftest dut: Add suport for RISCV vector extension difftest with spike
weidingliu Sep 21, 2023
17c24c2
difftest dut: Add suport for RISCV vector extension difftest with spike
weidingliu Sep 21, 2023
6a572ba
difftest dut: Add suport for RISCV vector extension difftest with spike
weidingliu Sep 21, 2023
d7ef7d7
delete some code
weidingliu Sep 22, 2023
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9 changes: 9 additions & 0 deletions include/cpu/difftest.h
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Original file line number Diff line number Diff line change
Expand Up @@ -48,5 +48,14 @@ static inline bool difftest_check_reg(const char *name, vaddr_t pc, rtlreg_t ref
}
return true;
}
static inline bool difftest_check_vreg(const char *name, vaddr_t pc, rtlreg_t *ref, rtlreg_t *dut,size_t n) {
/***************ONLY FOR VLEN=128,ELEN=64**********************/
if (memcmp(ref, dut, n)) {
Log("%s is different after executing instruction at pc = " FMT_WORD
", right = 0x%016lx_%016lx , wrong = %016lx_%016lx", name, pc, ref[1], ref[0], dut[1], dut[0]);
return false;
}
return true;
}

#endif
21 changes: 19 additions & 2 deletions src/isa/riscv64/difftest/dut.c
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Original file line number Diff line number Diff line change
Expand Up @@ -84,8 +84,25 @@ bool isa_difftest_checkregs(CPU_state *ref_r, vaddr_t pc) {
difftest_check_reg(reg_name(i, 4), pc, ref_r->gpr[i]._64, cpu.gpr[i]._64);
}
difftest_check_reg("pc", pc, ref_r->pc, cpu.pc);
#ifdef CONFIG_RVH
#ifdef CONFIG_RVV
for(i=0;i < ARRLEN(cpu.vr); i++){
difftest_check_vreg(vreg_name(i, 8), pc, ref_r->vr[i]._64, cpu.vr[i]._64,VLEN/8);
}
#endif // CONFIG_RVV

#define check_reg(r) difftest_check_reg(str(r), pc, ref_r->r, cpu.r)

#ifdef CONFIG_RVV
check_reg(vtype );
check_reg(vstart );
check_reg(vxsat );
check_reg(vxrm );
check_reg(vl );
check_reg(vcsr );
check_reg(vlenb );
#endif // CONFIG_RVV

#ifdef CONFIG_RVH
check_reg(v);//virtualization mode
check_reg(mstatus );
check_reg(mcause );
Expand Down Expand Up @@ -120,7 +137,7 @@ bool isa_difftest_checkregs(CPU_state *ref_r, vaddr_t pc) {
check_reg(vstval );
check_reg(vsatp );
check_reg(vsscratch );
#endif
#endif // CONFIG_RVH
return false;
}
return true;
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