fix(VecExcp): commit vls exception after Rab commiting all reg pairs

src/main/scala/xiangshan/backend/rob/Rab.scala

@@ -56,6 +56,7 @@ class RenameBuffer(size: Int)(implicit p: Parameters) extends XSModule with HasC
 
     val status = Output(new Bundle {
       val walkEnd = Bool()
+      val commitEnd = Bool()
     })
     val toVecExcpMod = Output(new RabToVecExcpMod)
   })
@@ -219,6 +220,7 @@ class RenameBuffer(size: Int)(implicit p: Parameters) extends XSModule with HasC
   }
 
   private val walkEndNext = walkSizeNxt === 0.U
+  private val commitEndNext = commitSizeNxt === 0.U
   private val specialWalkEndNext = specialWalkSize <= RabCommitWidth.U
   // when robWalkEndReg is 1, walkSize donot increase and decrease RabCommitWidth per Cycle
   private val walkEndNextCycle = (robWalkEndReg || io.fromRob.walkEnd && io.fromRob.walkSize === 0.U) && (walkSize <= RabCommitWidth.U)
@@ -263,6 +265,7 @@ class RenameBuffer(size: Int)(implicit p: Parameters) extends XSModule with HasC
   io.enqPtrVec := enqPtrVec
 
   io.status.walkEnd := walkEndNext
+  io.status.commitEnd := commitEndNext
 
   for (i <- 0 until RabCommitWidth) {
     io.toVecExcpMod.logicPhyRegMap(i).valid := (state === s_special_walk) && vecLoadExcp.valid &&

src/main/scala/xiangshan/backend/rob/Rob.scala

@@ -551,7 +551,8 @@ class RobImp(override val wrapper: Rob)(implicit p: Parameters, params: BackendP
   val deqHasReplayInst = deqNeedFlushAndHitExceptionGenState && exceptionDataRead.bits.replayInst
   val deqIsVlsException = deqHasException && deqPtrEntry.isVls && !exceptionDataRead.bits.isEnqExcp
   // delay 2 cycle wait exceptionGen out
-  deqVlsCanCommit := RegNext(RegNext(deqIsVlsException && deqPtrEntry.commit_w))
+  // vls exception can be committed only when RAB commit all its reg pairs
+  deqVlsCanCommit := RegNext(RegNext(deqIsVlsException && deqPtrEntry.commit_w)) && rab.io.status.commitEnd
 
   // lock at assertion of deqVlsExceptionNeedCommit until condition not assert
   val deqVlsExcpLock = RegInit(false.B)