rv64v: add clock gating to valid singal

OpenXiangShan · Mar 7, 2024 · 1def82c · 1def82c
1 parent 4823c6d
commit 1def82c
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Showing 9 changed files with 29 additions and 10 deletions.
diff --git a/src/main/scala/yunsuan/util/BitUtils.scala b/src/main/scala/yunsuan/util/BitUtils.scala
@@ -25,10 +25,10 @@ object RegNextWithEnable {
   def apply[T <: Data](data: Valid[T], hasInit: Boolean = true): Valid[T] = {
     val next = Wire(data.cloneType)
     if (hasInit) {
-      next.valid := RegNext(data.valid, false.B)
+      next.valid := GatedValidRegNext(data.valid, false.B)
     }
     else {
-      next.valid := RegNext(data.valid)
+      next.valid := GatedValidRegNext(data.valid)
     }
     next.bits := RegEnable(data.bits, data.valid)
     next

diff --git a/src/main/scala/yunsuan/util/ClockGatedReg.scala b/src/main/scala/yunsuan/util/ClockGatedReg.scala
@@ -0,0 +1,12 @@
+package yunsuan.util
+
+import chisel3._
+import chisel3.util._
+
+object GatedValidRegNext {
+  def apply(next: Bool, init: Bool = false.B): Bool = {
+    val last = Wire(next.cloneType)
+    last := RegEnable(next, init, next || last)
+    last
+  }
+}
diff --git a/src/main/scala/yunsuan/vector/VectorALU/VIAlu.scala b/src/main/scala/yunsuan/vector/VectorALU/VIAlu.scala
@@ -6,6 +6,7 @@ import chisel3.util._
 import yunsuan.vector._
 import yunsuan.vector.alu.VAluOpcode._
 import yunsuan.vector.alu.VSew._
+import yunsuan.util._
 
 class VIAlu extends Module {
   val io = IO(new Bundle {
@@ -14,7 +15,7 @@ class VIAlu extends Module {
   })
 
   // Latency of ALU is 1 cycles plus
-  io.out.valid := RegNext(io.in.valid)
+  io.out.valid := GatedValidRegNext(io.in.valid)
 
   val srcTypeVs1 = io.in.bits.srcType(1)
   val srcTypeVs2 = io.in.bits.srcType(0)

diff --git a/src/main/scala/yunsuan/vector/VectorConvert/CVT16.scala b/src/main/scala/yunsuan/vector/VectorConvert/CVT16.scala
@@ -4,6 +4,7 @@ import chisel3._
 import chisel3.util._
 import yunsuan.vector.VectorConvert.util._
 import yunsuan.vector.VectorConvert.RoundingModle._
+import yunsuan.util._
 
 
 class CVT16(width: Int = 16) extends CVT(width){
@@ -15,7 +16,7 @@ class CVT16(width: Int = 16) extends CVT(width){
    */
   // control path
   val fire = io.fire
-  val fireReg = RegNext(io.fire)
+  val fireReg = GatedValidRegNext(io.fire)
   val is_sew_8 = io.sew === "b00".U
   val is_sew_16 = io.sew === "b01".U
   val is_single = io.opType.tail(3).head(2) === "b00".U

diff --git a/src/main/scala/yunsuan/vector/VectorConvert/CVT32.scala b/src/main/scala/yunsuan/vector/VectorConvert/CVT32.scala
@@ -4,6 +4,7 @@ import chisel3._
 import chisel3.util._
 import yunsuan.vector.VectorConvert.util._
 import yunsuan.vector.VectorConvert.RoundingModle._
+import yunsuan.util._
 
 
 class CVT32(width: Int = 32) extends CVT(width){
@@ -15,7 +16,7 @@ class CVT32(width: Int = 32) extends CVT(width){
    */
   // control path
   val fire = io.fire
-  val fireReg = RegNext(io.fire)
+  val fireReg = GatedValidRegNext(io.fire)
   val is_sew_8  = io.sew === "b00".U
   val is_sew_16 = io.sew === "b01".U
   val is_sew_32 = io.sew === "b10".U

diff --git a/src/main/scala/yunsuan/vector/VectorConvert/CVT64.scala b/src/main/scala/yunsuan/vector/VectorConvert/CVT64.scala
@@ -5,6 +5,7 @@ import chisel3.util._
 import yunsuan.vector.VectorConvert.util._
 import yunsuan.vector.VectorConvert.utils._
 import yunsuan.vector.VectorConvert.RoundingModle._
+import yunsuan.util._
 
 class CVT64(width: Int = 64) extends CVT(width){
 
@@ -17,7 +18,7 @@ class CVT64(width: Int = 64) extends CVT(width){
   // input
   val (fire, src, sew, opType, rmNext, input1H, output1H) =
       (io.fire, io.src, io.sew, io.opType, io.rm, io.input1H, io.output1H)
-  val fireReg = RegNext(fire)
+  val fireReg = GatedValidRegNext(fire)
 
   // control for cycle 0
   val isWiden = !opType(4) && opType(3)

diff --git a/src/main/scala/yunsuan/vector/VectorConvert/Convert.scala b/src/main/scala/yunsuan/vector/VectorConvert/Convert.scala
@@ -3,6 +3,7 @@ package yunsuan.vector.VectorConvert
 import chisel3._
 import chisel3.util._
 import chisel3.util.experimental.decode._
+import yunsuan.util._
 
 class VectorCvtIO(width: Int) extends Bundle {
   val fire = Input(Bool())
@@ -68,7 +69,7 @@ class VectorCvt(xlen :Int) extends Module{
   dontTouch(output1H)
 
   val inputWidth1H = input1H
-  val outputWidth1H = RegEnable(RegEnable(output1H, fire), RegNext(fire))
+  val outputWidth1H = RegEnable(RegEnable(output1H, fire), GatedValidRegNext(fire))
 
 
   val element8 = Wire(Vec(8,UInt(8.W)))

diff --git a/src/main/scala/yunsuan/vector/VectorFloatFMA.scala b/src/main/scala/yunsuan/vector/VectorFloatFMA.scala
@@ -4,6 +4,7 @@ import chisel3._
 import chisel3.util._
 import scala.collection.mutable.ListBuffer
 import yunsuan.VfmaOpCode
+import yunsuan.util._
 
 class VectorFloatFMA() extends Module{
   val exponentWidth : Int = 11
@@ -55,8 +56,8 @@ class VectorFloatFMA() extends Module{
     if (printfen) printf(pable)
   }
   val fire = io.fire
-  val fire_reg0 = RegNext(fire)
-  val fire_reg1 = RegNext(fire_reg0)
+  val fire_reg0 = GatedValidRegNext(fire)
+  val fire_reg1 = GatedValidRegNext(fire_reg0)
   val is_vfmul   = io.op_code === VfmaOpCode.vfmul
   val is_vfmacc  = io.op_code === VfmaOpCode.vfmacc
   val is_vfnmacc = io.op_code === VfmaOpCode.vfnmacc

diff --git a/src/main/scala/yunsuan/vector/vectorIMAC/VIMac64b.scala b/src/main/scala/yunsuan/vector/vectorIMAC/VIMac64b.scala
@@ -3,6 +3,7 @@ package yunsuan.vector.mac
 import chisel3._
 import chisel3.util._
 import yunsuan.vector._
+import yunsuan.util._
 
 /** 64-bit vector multiply and accumlation unit
  *  
@@ -29,7 +30,7 @@ class VIMac64b extends Module {
   })
 
   val fire = io.fire
-  val fireS1 = RegNext(fire)
+  val fireS1 = GatedValidRegNext(fire)
   val vs2 = io.vs2
   val vs1 = io.vs1
   val oldVd = io.oldVd