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fix(fma): Fix the misuse of pipeline registers #173

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Dec 21, 2024
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fix(fma): Fix the misuse of pipeline registers #173

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6 changes: 3 additions & 3 deletions src/main/scala/yunsuan/fpu/FloatFMA.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -476,9 +476,9 @@ class FloatFMA() extends Module{
Mux(is_fp32_reg1, fraction_result_no_round_f32_reg_d, fraction_result_no_round_f16_reg_d))
val fraction_result_no_round_reg = RegEnable(fraction_result_no_round_reg_d, fire_reg1)

val fraction_result_no_round_f64_reg2 = fraction_result_no_round_reg_d
val fraction_result_no_round_f32_reg2 = fraction_result_no_round_reg_d(22,0)
val fraction_result_no_round_f16_reg2 = fraction_result_no_round_reg_d(9,0)
val fraction_result_no_round_f64_reg2 = fraction_result_no_round_reg
val fraction_result_no_round_f32_reg2 = fraction_result_no_round_reg(22,0)
val fraction_result_no_round_f16_reg2 = fraction_result_no_round_reg(9,0)

val fraction_result_round_f64 = fraction_result_no_round_f64_reg2 +& 1.U
val fraction_result_round_f32 = fraction_result_no_round_f32_reg2 +& 1.U
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