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[Paddle-TRT] Implement MHA fp16 order same as training #32629

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merged 4 commits into from
Apr 29, 2021
Merged

[Paddle-TRT] Implement MHA fp16 order same as training #32629

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4374fa4
implement MHA order same as training
zlsh80826 Apr 27, 2021
6206a21
fix fp16 compile issue on old architecture
zlsh80826 Apr 28, 2021
757129b
fix format
zlsh80826 Apr 28, 2021
4fd3118
fix format
zlsh80826 Apr 28, 2021
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17 changes: 16 additions & 1 deletion paddle/fluid/inference/tensorrt/plugin/qkv_to_context_plugin.cu
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Original file line number Diff line number Diff line change
Expand Up @@ -225,6 +225,14 @@ nvinfer1::DataType QkvToContextPluginDynamic::getOutputDataType(
return input_types[0];
}

template <typename T>
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__global__ void apply_scale(T *data, T scale, int n) {
#if CUDA_ARCH_FP16_SUPPORTED(__CUDA_ARCH__)
int tid = blockIdx.x * blockDim.x + threadIdx.x;
data[tid] = data[tid] * scale;
#endif
}

int QkvToContextPluginDynamic::enqueue(
const nvinfer1::PluginTensorDesc *input_desc,
const nvinfer1::PluginTensorDesc *output_desc, const void *const *inputs,
Expand Down Expand Up @@ -291,10 +299,17 @@ int QkvToContextPluginDynamic::enqueue(
platform::DeviceContextPool::Instance().Get(
platform::CUDAPlace(device_id)));

int n_q = seq_len * head_number_ * head_size_;
constexpr int threads = 128;
int blocks = (n_q + threads - 1) / threads;

apply_scale<<<blocks, threads, 0, stream>>>(tptr, static_cast<half>(scale_),
n_q);

const platform::CUDADeviceContext &dev_ctx = *device_ctx;
operators::math::MultiHeadGPUComputeFunctor<half> multihead_compute_func;
multihead_compute_func(dev_ctx, batch, seq_len, head_number_, head_size_,
qkptr, input1_data, tptr, half(scale_), half(0.0));
qkptr, input1_data, tptr, half(1.), half(0.0));

int grid = batch * head_number_ * seq_len;
int block = head_size_;
Expand Down