multicore: remove coherence units

[devins2518]

The coherence units add unnecessary latency and logic to bus requests. This PR removes the middle man and directly integrates the bus_controller into l1_cache. With this change, it will be easier to debug coherence/deadlock issues, and (this is purely speculative) reduce the ability to deadlock due to interoperating FSMs (cache, coherence unit, bus). The coherence stress test continues to work fine, and riscv-tests continue to pass.

One thing I want to change before merging is the hit logic for writes. Currently, there's an extremely nasty edge case where if a write request is started during a snoop hit, it will lower proc_gen_bus_if.busy before actually writing to the SRAM. This should only affect things which are able to lower ren/wen on the negative edge of the clock, however, I'm sure there's a better way to represent this logic that I can't think of right now.

Performance

In merge sort, there is a ~5% speedup over the previous design. For the global_atomic toy test which tests atomic addition on a highly contentious variable, speedup is ~10%. There is likely still performance that can be squeezed out of the memory subsystem, however, its out of the scope of this PR.