updated source files

src/AHBUart_dependencies.sv

@@ -164,6 +164,8 @@ module BaudRateGen #(
     if (!nReset) begin
       // txCount <= rate - 1;
       txCount <= 0;
+	end else if (txCount == 0) begin
+		txCount <= rate - 1;
     end else begin
       txCount <= txCount - 1;
     end

src/AHBUart_tapeout.sv

@@ -25,9 +25,7 @@
 //uart implementation
 
 module AHBUart_tapeout #(
-    logic [19:0] DefaultRate = 5207  // Chosen by fair dice roll
-    //Michael - i don't like this number :( 
-    //Yash - my bad ..?
+	logic [19:0] DefaultRate = 5207  // value for 9600 baudrate
 ) (
     input clk, 
     input nReset, 
@@ -49,7 +47,7 @@ module AHBUart_tapeout #(
     logic [1:0] rate_control, ren_wen;
     logic [19:0] rate, new_rate;
     logic [1:0]  ren_wen_nidle, prev_ren_wen; // act as the direction
-    assign ren_wen = control[3:2];
+	assign ren_wen = control[3:2];
     assign rate_control = control[1:0];
     // tristate logic handling...
 
@@ -78,10 +76,12 @@ module AHBUart_tapeout #(
     end
 
   always_comb begin
+	  //"rate" is defined as the amount of clock cycles between each bit send/received by UART
+	  //calculation is clock cycle/baudrate 
         case(rate_control)
-            2'b01: new_rate = 9600;
-            2'b10: new_rate = 50000;
-            2'b11: new_rate = 115200;
+            2'b01: new_rate = 2604;			//value for 19200 baudrate
+            2'b10: new_rate = 1302;			//value for 38400 baudrate
+            2'b11: new_rate = 434;			//value for 115200 baudrate
             default: new_rate = DefaultRate;
         endcase
     end

src/sv2v_converted/AHBUart_tapeout.v

@@ -47,9 +47,9 @@ module AHBUart_tapeout (
 		if (_sv2v_0)
 			;
 		case (rate_control)
-			2'b01: new_rate = 9600;
-			2'b10: new_rate = 50000;
-			2'b11: new_rate = 115200;
+			2'b01: new_rate = 2604;
+			2'b10: new_rate = 1302;
+			2'b11: new_rate = 434;
 			default: new_rate = DefaultRate;
 		endcase
 	end

src/sv2v_converted/BaudRateGen.v

@@ -55,6 +55,8 @@ module BaudRateGen (
 	always @(posedge clk or negedge nReset)
 		if (!nReset)
 			txCount <= 0;
+		else if (txCount == 0)
+			txCount <= rate - 1;
 		else
 			txCount <= txCount - 1;
 	initial _sv2v_0 = 0;

src/sv2v_converted/socetlib_fifo.v

@@ -28,7 +28,7 @@ module socetlib_fifo (
 	output wire [7:0] rdata;
 	generate
 		if ((DEPTH == 0) || ((DEPTH & (DEPTH - 1)) != 0)) begin : genblk1
-			$error("%m: DEPTH must be a power of 2 >= 1!");
+			initial $display("Error [elaboration] src/AHBUart_dependencies.sv:25:13 - socetlib_fifo.genblk1\n msg: ", "%m: DEPTH must be a power of 2 >= 1!");
 		end
 	endgenerate
 	localparam signed [31:0] ADDR_BITS = $clog2(DEPTH);