Remove references to skip_transpilation (#1121)

closes #1119

docs/run/quantum-serverless.mdx

@@ -131,7 +131,7 @@ Instead of manually selecting a system, step 2 of the Qiskit Pattern optimizes t
 
 For each `IBMQPUSelector`, the context is set in the constructor. All `IBMQPUSelectors` require Qiskit Runtime credentials. The `IBMLeastNoisyQPUSelector` requires a circuit and transpile options specifying how the circuit should be optimized for each system when determining the most optimal QPU and qubit layout. All `IBMQPUSelector`s implement a `get_backend` method, which retrieves the optimal system with respect to the given context. The `get_backend` method also allows for additional filtering of the systems. It is implemented using the same interface as the [QiskitRuntimeService.backends method](/api/qiskit-ibm-runtime/qiskit_ibm_runtime.QiskitRuntimeService#backends).
 
-Then, in step 3 of the pattern, you execute the target circuit on the system chosen by the selector. Since you optimized your circuit for the system in step 2, you can skip transpilation in the primitives by setting `skip_transpilation=True`. 
+Then, in step 3 of the pattern, you execute the target circuit on the system chosen by the selector. Since you optimized your circuit for the system in step 2, you can skip further optimization in the primitives by setting `optimization_level=0`. 
 
 <Tabs>
   <TabItem value="SamplerV2" label="Sampler V2">

docs/transpile/dynamical-decoupling-pass-manager.ipynb

@@ -250,7 +250,7 @@
    "id": "69c77b6c-1f38-4adc-9249-0039ecd2c3c1",
    "metadata": {},
    "source": [
-    "Now, `YGate`s are absent from our circuit, and there is explicit timing information in the form of `Delay` gates. This transpiled circuit with dynamical decoupling is not ready to be sent to the backend. When doing so, remember to set the `skip_transpilation=True` option (See [Advanced runtime compilation options](/run/configure-runtime-compilation#advanced-runtime-compilation-options))."
+    "Now, `YGate`s are absent from our circuit, and there is explicit timing information in the form of `Delay` gates. This transpiled circuit with dynamical decoupling is not ready to be sent to the backend."
    ]
   },
   {

docs/transpile/index.mdx

@@ -25,11 +25,11 @@ Find more information about the pass manager stages in the [Transpiler stages](t
 
 
 ### Instruction set architecture
-In addition to reducing the depth and complexity of quantum circuits, the transpiler is designed to transform the instructions contained in a given `QuantumCircuit` to obey the **Instruction Set Architecture** (**ISA**) of a particular backend.  Circuits obeying the ISA consist only of instructions which are supported by the backend's [`Target`](../api/qiskit/qiskit.transpiler.Target) (e.g. the hardware's available basis gates, measurements, resets, control flow operations, etc.) and comply with the constraints specified by the connectivity of the hardware (i.e. the target's [`CouplingMap`](../api/qiskit/qiskit.transpiler.CouplingMap)).  When using Qiskit Runtime to submit a job to an IBM Quantum™ backend, the circuits must adhere to the backend's ISA. 
+In addition to reducing the depth and complexity of quantum circuits, the transpiler is designed to transform the instructions contained in a given `QuantumCircuit` to obey the Instruction Set Architecture (ISA) of a particular backend.  Circuits obeying the ISA consist only of instructions that are supported by the backend's [`Target`](../api/qiskit/qiskit.transpiler.Target), such as the hardware's available basis gates, measurements, resets, and control flow operations, and comply with the constraints specified by the connectivity of the hardware, that is, the target's [`CouplingMap`](../api/qiskit/qiskit.transpiler.CouplingMap).  When submitting a job to an IBM Quantum™ backend, the circuits must adhere to the backend's ISA. 
 
 
 <Admonition type="caution">
-  If you perform transpilation locally and submit the transpiled circuits to the Qiskit Runtime service, the service will attempt to apply additional optimizations by default, corresponding to `optimization_level=1` described [here](/run/configure-runtime-compilation#set-the-optimization-level). If you do not wish to have your circuits further transformed, set the `skip_transpilation` option to `True` to indicate to the service not to apply these optimizations (see [Advanced runtime compilation options](/run/configure-runtime-compilation#advanced-runtime-compilation-options)). However, note that all circuits submitted to the Qiskit Runtime service must be composed of instructions supported by the system's Instruction Set Architecture (ISA); otherwise, the jobs will fail.
+  If you perform transpilation locally and submit the transpiled circuits to the Qiskit Runtime service, the service tries to apply additional optimizations by default, corresponding to `optimization_level=1` described [here](/run/configure-runtime-compilation#set-the-optimization-level). If you do not want the circuits further transformed, set the optimization_level to 0. 
 </Admonition>
 
 
@@ -39,7 +39,7 @@ Qiskit's prebuilt transpiler pipeline consists of six fundamental stages:
 
 1. `init` - This pass runs any initial passes that are required before we start embedding the circuit to the system.  This typically involves unrolling custom instructions and converting the circuit to all single- and two-qubit gates. (By default this will just validate the circuit instructions and translate multi-qubit gates into single- and two-qubit gates.)
 1. `layout` - This pass applies a *layout*, mapping/assigning the virtual qubits in your circuit to the physical qubits of a system.
-1. `routing` - This pass runs after a layout has been applied and will inject gates (i.e., SWAPs) in the original circuit in order to make it compatible with the system's connectivity/coupling map.
+1. `routing` - This pass runs after a layout has been applied and will inject gates (that is, SWAPs) in the original circuit in order to make it compatible with the system's connectivity/coupling map.
 1. `translation` - This pass translates the gates in the circuit to the system's basis set of instructions.
 1. `optimization` - This pass runs an optimization loop to find more efficient decompositions of your quantum circuit until a condition is met (such as a fixed depth).
 1. `scheduling` - This stage is for any hardware-aware scheduling passes. If the user specifies a scheduling method, this stage accounts for all idle time in the circuit.