Fix barrier label position when bits are reversed

[atharva-satpute]

Summary

Fixes: #13609
Changed the way the barrier label is applied to qubits. Previously, we used the index of the qubit in qargs list to decide if a label should be added here. Now, the label is applied to the qubit with the smallest index in _wire_map, ensuring the label is based on the qubit's position in the _wire_map rather than its position in the node.qargs list

Details and comments

Output:

      init ┌───┐      final 
q_0: ──░───┤ H ├──■─────░───
       ░   └───┘┌─┴─┐   ░   
q_1: ──░────────┤ X ├───░───
       ░        └───┘   ░   
      init      ┌───┐ final 
q_1: ──░────────┤ X ├───░───
       ░   ┌───┐└─┬─┘   ░   
q_0: ──░───┤ H ├──■─────░───
       ░   └───┘        ░   

[qiskit-bot]

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[jakelishman]

This looks like the start of a solid change. The tests are showing trouble in barriers that aren't full width (e.g. the top of the barrier isn't at the top of the drawing), so I think we might need some logic a bit more along the lines of

top_qubit = min(node.qargs, key=self._wire_map.get)
for qubit in node.qargs:
    if qubit in self.qubits:
        label = op.label if qubit == top_qubits else ""
        # ...

(completely untested) to handle those cases.

Please could you also add a test case that's a regression test of what you're fixing, and a bugfix release note?

[atharva-satpute]

This looks like the start of a solid change. The tests are showing trouble in barriers that aren't full width (e.g. the top of the barrier isn't at the top of the drawing), so I think we might need some logic a bit more along the lines of

top_qubit = min(node.qargs, key=self._wire_map.get)
for qubit in node.qargs:
    if qubit in self.qubits:
        label = op.label if qubit == top_qubits else ""
        # ...

(completely untested) to handle those cases.

Please could you also add a test case that's a regression test of what you're fixing, and a bugfix release note?

I’ve set the default value to float("inf") for cases where the qubit isn’t found in self._wire_map, which can happen when idle_wires = False

[coveralls]

Pull Request Test Coverage Report for Build 13157633583

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Details

• 3 of 3 (100.0%) changed or added relevant lines in 1 file are covered.
• 243 unchanged lines in 19 files lost coverage.
• Overall coverage decreased (-0.1%) to 88.657%

---

Files with Coverage Reduction	New Missed Lines	%
crates/circuit/src/dag_circuit.rs	1	89.36%
qiskit/providers/fake_provider/fake_backend.py	1	85.51%
qiskit/providers/basic_provider/basic_provider_tools.py	1	83.33%
crates/circuit/src/operations.rs	1	89.61%
qiskit/pulse/transforms/canonicalization.py	1	93.44%
qiskit/pulse/transforms/base_transforms.py	2	86.96%
qiskit/pulse/schedule.py	3	88.6%
qiskit/result/result.py	3	83.74%
qiskit/providers/models/backendconfiguration.py	3	85.76%
qiskit/circuit/library/blueprintcircuit.py	3	96.52%

Totals
Change from base Build 13115148220:	-0.1%
Covered Lines:	78953
Relevant Lines:	89054

---

💛 - Coveralls

[qiskit-bot]

Thank you for opening a new pull request.

Before your PR can be merged it will first need to pass continuous integration tests and be reviewed. Sometimes the review process can be slow, so please be patient.

While you're waiting, please feel free to review other open PRs. While only a subset of people are authorized to approve pull requests for merging, everyone is encouraged to review open pull requests. Doing reviews helps reduce the burden on the core team and helps make the project's code better for everyone.

One or more of the following people are relevant to this code:

• @enavarro51
• @Qiskit/terra-core

[jakelishman]

Ace, thank you!

[johnbhurst]

Hmm. Using Qiskit 1.4.1, and the sample code I put in the original ticket 13609:

from qiskit.circuit import QuantumCircuit, QuantumRegister

q = [q0, q1] = QuantumRegister(2, 'q')
circuit = QuantumCircuit(q)
circuit.barrier(label='init')
circuit.h(q0)
circuit.cx(q0, q1)
circuit.barrier(label='final')
circuit.draw(output='mpl', filename='circuit.png')
circuit.draw(output='mpl', filename='circuit_reverse_bits.png', reverse_bits=True)

I am still getting the same incorrect barrier label positions as shown in the images in the original ticket.

Am I missing something?

[atharva-satpute]

I missed adding changes for output="mpl" and others. I'll submit a new PR soon

[atharva-satpute]

Created #13971