Check the existence of AncillaQubits before adding #7450
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Also appears to be blocked by #7457 |
jakelishman
requested changes
Jan 4, 2022
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| def test_add_existing_bits(self): | ||
| """Test add registers whose bits have already been added.""" | ||
| qc = QuantumCircuit() | ||
| for bit_type, reg_type in ( | ||
| [Qubit, QuantumRegister], | ||
| [Clbit, ClassicalRegister], | ||
| [AncillaQubit, AncillaRegister], | ||
| ): | ||
| bits = [bit_type() for _ in range(10)] | ||
| reg = reg_type(bits=bits) | ||
| qc.add_bits(bits) | ||
| qc.add_register(reg) | ||
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| self.assertEqual(qc.num_qubits, 20) | ||
| self.assertEqual(qc.num_clbits, 10) | ||
| self.assertEqual(qc.num_ancillas, 10) | ||
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Please could we add a test that calling add_register with two different AncillaRegisters containing the same bits, without calling add_bits at all, also adds the correct number of bits? With this PR it will succeed, because AncillaRegister derives from QuantumRegister, but it'd be good to ensure that it's always the case - we can't rely on add_bits having been called by the user first.
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I see. It has been added with the name test_overlapped_add_register_and_add_register
jakelishman
added
Changelog: Bugfix
Pull Request Test Coverage Report for Build 1731098913
💛 - Coveralls |
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@jakelishman Sure. The release note had been added. |
jakelishman
approved these changes
Jan 20, 2022
kdk
approved these changes
Jan 21, 2022
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Jan 21, 2022
* Check the existance of AncillaQubits before adding * Add a test case that calls add_register twice * Add a release note * Reword release note Co-authored-by: Jake Lishman <jake.lishman@ibm.com> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> Co-authored-by: Kevin Krsulich <kevin.krsulich@ibm.com> (cherry picked from commit 84c3985)
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Jan 22, 2022
* Check the existance of AncillaQubits before adding * Add a test case that calls add_register twice * Add a release note * Reword release note Co-authored-by: Jake Lishman <jake.lishman@ibm.com> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> Co-authored-by: Kevin Krsulich <kevin.krsulich@ibm.com> (cherry picked from commit 84c3985) Co-authored-by: Jintao YU <yjt98765@gmail.com>
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Summary
The bits in an
AncillaRegisterare appended toQuantumCircuit._ancillawithout checking:https://github.com/Qiskit/qiskit-terra/blob/9cc9225f249d3a895d9f3944175ea7b681d248c0/qiskit/circuit/quantumcircuit.py#L1354-L1355
This caused the issue described in #7445.
Details and comments
I fix this problem by checking the existence of
AncillaQubitbefore the appending, which is similar to the operation regardingQuantumRegister. A test case is added to demonstrate the change. The test failed without the modification.close #7445