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* Adding AEC App * Adding wifi folder * Adding new I2S data grabbing files * Removed GPIO_1 from Power since it is used for I2S indication * Adding ESP32 binary * Adding ESP32 bin files * Added files fixed for GCC project * Made some changes to to be able to compile for GCC * Removed the FPGA bitfile compiled using Open source tools and enabled SPDE compiled bitfile * Changed the README.rst file to include AEC info * updated qf_vr_aec_app gcc build to use QORC_TC_PATH variable * Adding the latest GCC compiled QuickFeather binary to Huzzah32 binary * Removed backup files in inc folder * Fixed FLL file Co-authored-by: Siva Kumar Perugu <sperugu@quicklogic.com>
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| Original file line number | Diff line number | Diff line change |
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| /*========================================================== | ||
| * Copyright 2021 QuickLogic Corporation | ||
| * | ||
| * Licensed under the Apache License, Version 2.0 (the "License"); | ||
| * you may not use this file except in compliance with the License. | ||
| * You may obtain a copy of the License at | ||
| * | ||
| * http://www.apache.org/licenses/LICENSE-2.0 | ||
| * | ||
| * Unless required by applicable law or agreed to in writing, software | ||
| * distributed under the License is distributed on an "AS IS" BASIS, | ||
| * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. | ||
| * See the License for the specific language governing permissions and | ||
| * limitations under the License. | ||
| *==========================================================*/ | ||
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| /*========================================================== | ||
| * | ||
| * File : eoss3_hal_fpga_decimation_fir.h | ||
| * Purpose: This file contains FIR functions for Rx data in fpga. | ||
| * | ||
| *=========================================================*/ | ||
| #include "Fw_global_config.h" | ||
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| #ifndef __EOSS3_HAL_FB_DECIMATION_FIR_H_ | ||
| #define __EOSS3_HAL_FB_DECIMATION_FIR_H_ | ||
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| #include "eoss3_dev.h" | ||
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| #define FB_DECIMATION_FIR_REG_OFFSET (FPGA_PERIPH_BASE + 0x4000 + 0x1000) | ||
| #define FB_DECIMATION_FIR_SDMA_BASE (FPGA_PERIPH_BASE + 0x4000) | ||
| #define FB_FIR_SDMA ((FIR_SDMA_TypeDef *) FB_DECIMATION_FIR_SDMA_BASE) | ||
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| typedef struct | ||
| { | ||
| __IO uint32_t FIR_IER; /*0x00 I2S Enable Register */ | ||
| __IO uint32_t FIR_ACSLIPR; /*0x04 ACSLIP Reset (deprecated)*/ | ||
| __IO uint32_t FIR_ISR; /*0x08 Interrupt Status Register */ | ||
| __IO uint32_t FIR_IEN; /*0x0C Interrupt Enable Register */ | ||
| __IO uint32_t FIR_DFSTS; /*0x10 Decimation FIFO Status Register */ | ||
| __IO uint32_t FIR_DFDREG; /*0x14 Decimation Data Register */ | ||
| __IO uint32_t FIR_ACSLIP; /*0x18 ACSLIP Register (deprecated) */ | ||
| __IO uint32_t FIR_DFRST; /*0x1C Decimation FIFO Reset Register */ | ||
| __IO uint32_t FIR_DER; /*0x20 DMA Enable Register */ | ||
| __IO uint32_t FIR_DSR; /*0x24 DMA Status Register */ | ||
| __IO uint32_t FIR_DCNT; /*0x28 DMA Count Register */ | ||
| __IO uint32_t FIR_ACSLTMR; /*0x2C ACSLIP Timer (deprecated) */ | ||
| __IO uint32_t FIR_FDCR; /*0x30 FIR Decimation Control Register */ | ||
| __IO uint32_t FIR_FDSR; /*0x34 FIR Decimation Status Register */ | ||
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| __IO uint32_t FIR_RSRVD1; /*0x38 Reserved 1 */ | ||
| __IO uint32_t FIR_RSRVD2; /*0x3c Reserved 2 */ | ||
| __IO uint32_t FIR_FIFO; /*0x40 FIR FIFO Status Register */ | ||
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| } FIR_SDMA_TypeDef; | ||
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| extern void HAL_FIR_Decimation_FB_SDMA_Config(void); | ||
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| extern uint8_t is_fir_fb_slave_dma_done_intr_set(void); | ||
| extern void fir_fb_slave_rx_dma_done_clear(void); | ||
| extern void fir_fb_slave_rx_dma_en(void); | ||
| extern void HAL_FIR_Decimation_Stop (void); | ||
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| #endif //__EOSS3_HAL_FB_DECIMATION_FIR_H_ |
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| /*========================================================== | ||
| * Copyright 2021 QuickLogic Corporation | ||
| * | ||
| * Licensed under the Apache License, Version 2.0 (the "License"); | ||
| * you may not use this file except in compliance with the License. | ||
| * You may obtain a copy of the License at | ||
| * | ||
| * http://www.apache.org/licenses/LICENSE-2.0 | ||
| * | ||
| * Unless required by applicable law or agreed to in writing, software | ||
| * distributed under the License is distributed on an "AS IS" BASIS, | ||
| * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. | ||
| * See the License for the specific language governing permissions and | ||
| * limitations under the License. | ||
| *==========================================================*/ | ||
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| /*========================================================== | ||
| * | ||
| * File : eoss3_hal_fpga_i2s_slave.h | ||
| * Purpose: This file contains API declaration for I2S Slave | ||
| * Rx implemented in fpga. | ||
| * | ||
| *=========================================================*/ | ||
| #include "Fw_global_config.h" | ||
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| #ifndef __EOSS3_HAL_FB_I2S_SLAVE_H_ | ||
| #define __EOSS3_HAL_FB_I2S_SLAVE_H_ | ||
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| #include "eoss3_dev.h" | ||
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| #define FB_I2S_SDMA_BASE (FPGA_PERIPH_BASE + 0x2000) | ||
| #define FB_I2S_REG_OFFSET (FPGA_PERIPH_BASE + 0x2000 + 0x1000) | ||
| #define FB_I2S_SDMA ((I2S_SDMA_TypeDef *) FB_I2S_REG_OFFSET) | ||
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| typedef struct | ||
| { | ||
| __IO uint32_t I2S_IER; /*0x00 I2S Enable Register */ | ||
| __IO uint32_t I2S_ACSLIPR; /*0x04 ACSLIP Reset (deprecated)*/ | ||
| __IO uint32_t I2S_ISR; /*0x08 Interrupt Status Register */ | ||
| __IO uint32_t I2S_IEN; /*0x0C Interrupt Enable Register */ | ||
| __IO uint32_t I2S_DFSTS; /*0x10 Decimation FIFO Status Register */ | ||
| __IO uint32_t I2S_DFDREG; /*0x14 Decimation Data Register */ | ||
| #if 0 | ||
| __IO uint32_t I2S_ACSLIP; /*0x18 ACSLIP Register (deprecated) */ | ||
| __IO uint32_t I2S_DFRST; /*0x1C Decimation FIFO Reset Register */ | ||
| __IO uint32_t I2S_DER; /*0x20 DMA Enable Register */ | ||
| __IO uint32_t I2S_DSR; /*0x24 DMA Status Register */ | ||
| __IO uint32_t I2S_DCNT; /*0x28 DMA Count Register */ | ||
| __IO uint32_t I2S_ACSLTMR; /*0x2C ACSLIP Timer (deprecated) */ | ||
| __IO uint32_t I2S_FDCR; /*0x30 FIR Decimation Control Register */ | ||
| __IO uint32_t I2S_FDSR; /*0x34 FIR Decimation Status Register */ | ||
| #endif | ||
| } I2S_SDMA_TypeDef; | ||
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| extern void eoss3_hal_fabric_i2s_slave_clks_disable(); | ||
| extern void eoss3_hal_fabric_i2s_slave_clks_enable(); | ||
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| extern void HAL_FB_I2SRx_Ref_input_DmaStart(void); | ||
| extern void HAL_FB_I2SRx_Ref_input_DmaNext(void); | ||
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| #endif //__EOSS3_HAL_FB_I2S_SLAVE_H_ |
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