Merge #19777 #19798

19777: cpu/avr8_common: Prepare for rework ISR r=benpicco a=nandojve

### Contribution description

This prepares for rework how ISR is handled for AVR-8 platform. It is not expected changes on the behavior but tests on other boards were welcome to avoid regressions.

#### Improvements
 * Split UART state from ISR states. Now it is necessary two variables and GPIORx registers are automatically selected when available.
 * UART states now supports up to 8 UARTs.
 * Added AVR8_ISR macro do clean-up and hide internals related to ISR processing. This allows changes on ISR without any other changes on drivers.

### Testing procedure

Tests were conducted using atmega328p-xplained-mini and atxmega-a1u-xpro and the zigduino board was only built. The example thread_duel was used to test regressions.

19798: cpu/nrf53: add I2C and SPI support r=benpicco a=dylad

### Contribution description

This PR provides support for nRF53 SPI and I2C.
It also moves common structs from each nRF CPU folder to `cpu/nrf5x_common` to avoid duplication.
Moreover, since nRF9160 and nRF5340 have shared IRQ for UART/SPI/I2C. Both this families now use a common file to register and manage these interrupts. Note that nRF9160 have different name for its interrupts than nRF5340 but they have the same purpose.

### Testing procedure

Since some structs were moved around, I think this PR should be carefully tested against nRF52, nRF53 and nRF9160 to avoid any issues.
On nRF5340DK-APP, SPI can be tested with its onboard SPI flash.

### Issues/PRs references



Co-authored-by: Gerson Fernando Budke <nandojve@gmail.com>
Co-authored-by: Dylan Laduranty <dylan.laduranty@mesotic.com>

boards/nrf5340dk-app/Makefile.dep

@@ -0,0 +1,9 @@
+ifneq (,$(filter mtd,$(USEMODULE)))
+  USEMODULE += mtd_spi_nor
+endif
+
+# default to using littlefs2 on the external flash
+ifneq (,$(filter vfs_default,$(USEMODULE)))
+  USEPKG += littlefs2
+  USEMODULE += mtd
+endif

boards/nrf5340dk-app/Makefile.features

@@ -2,8 +2,10 @@ CPU_MODEL = nrf5340_app
 CPU = nrf53
 
 # Put defined MCU peripherals here (in alphabetical order)
+FEATURES_PROVIDED += periph_i2c
 FEATURES_PROVIDED += periph_pwm
 FEATURES_PROVIDED += periph_rtt
+FEATURES_PROVIDED += periph_spi
 FEATURES_PROVIDED += periph_timer
 FEATURES_PROVIDED += periph_uart
 FEATURES_PROVIDED += periph_uart_hw_fc

boards/nrf5340dk-app/board.c

@@ -0,0 +1,58 @@
+/*
+ * Copyright (C) 2023 Mesotic SAS
+ *
+ * This file is subject to the terms and conditions of the GNU Lesser
+ * General Public License v2.1. See the file LICENSE in the top level
+ * directory for more details.
+ */
+
+/**
+ * @ingroup     boards_nrf5340dk-app
+ * @{
+ *
+ * @file
+ * @brief       Board specific implementations for the Nordic nRF5340DK board
+ *
+ * @author      Dylan Laduranty <dylan.laduranty@mesotic.com>
+ * @}
+ */
+
+#include "board.h"
+#include "periph/gpio.h"
+#include "timex.h"
+#ifdef MODULE_VFS_DEFAULT
+#include "vfs_default.h"
+#endif
+
+#ifdef MODULE_MTD_SPI_NOR
+#include "mtd_spi_nor.h"
+/* MX25R64 */
+static const mtd_spi_nor_params_t _nrf5340_nor_params = {
+    .opcode = &mtd_spi_nor_opcode_default,
+    .wait_chip_erase = 240 * US_PER_SEC,
+    .wait_64k_erase = 800 * US_PER_MS,
+    .wait_sector_erase = 240 * US_PER_MS,
+    .wait_chip_wake_up = 1 * US_PER_MS,
+    .clk  = MHZ(54),
+    .flag = SPI_NOR_F_SECT_4K | SPI_NOR_F_SECT_64K,
+    .spi  = SPI_DEV(0),
+    .mode = SPI_MODE_0,
+    .cs   = BOARD_QSPI_PIN_CS,
+    .wp   = BOARD_QSPI_PIN_WP,
+    .hold = BOARD_QSPI_PIN_HOLD,
+};
+
+static mtd_spi_nor_t nrf5340_nor_dev = {
+    .base = {
+        .driver = &mtd_spi_nor_driver,
+        .page_size = 256,
+        .pages_per_sector = 16,
+    },
+    .params = &_nrf5340_nor_params,
+};
+mtd_dev_t *mtd0 = (mtd_dev_t *)&nrf5340_nor_dev;
+
+#ifdef MODULE_VFS_DEFAULT
+VFS_AUTO_MOUNT(littlefs2, VFS_MTD(nrf5340_nor_dev), VFS_DEFAULT_NVM(0), 0);
+#endif
+#endif /* MODULE_MTD_SPI_NOR */

boards/nrf5340dk-app/include/board.h

@@ -20,6 +20,7 @@
 #define BOARD_H
 
 #include "cpu.h"
+#include "mtd.h"
 
 #ifdef __cplusplus
 extern "C" {
@@ -95,6 +96,19 @@ extern "C" {
 #define BTN3_MODE           GPIO_IN_PU       /**< BTN3 default mode */
 /** @} */
 
+/**
+ * @name MTD configuration
+ * @{
+ */
+extern mtd_dev_t *mtd0;
+#define MTD_0       mtd0
+#define MTD_NUMOF   1
+
+#define BOARD_QSPI_PIN_CS       GPIO_PIN(0, 18)     /**< SPI Flash Chip Select */
+#define BOARD_QSPI_PIN_WP       GPIO_PIN(0, 15)     /**< SPI Flash Write Protect */
+#define BOARD_QSPI_PIN_HOLD     GPIO_PIN(0, 16)     /**< SPI Flash Hold pin */
+/** @} */
+
 #ifdef __cplusplus
 }
 #endif

boards/nrf5340dk-app/include/periph_conf.h

@@ -70,8 +70,6 @@ static const uart_conf_t uart_config[] = {
     },
 };
 
-#define UART_0_ISR          (isr_serial0) /**< SERIAL0_IRQn */
-
 #define UART_NUMOF          ARRAY_SIZE(uart_config) /**< UART configuration NUMOF */
 /** @} */
 
@@ -112,6 +110,22 @@ static const pwm_conf_t pwm_config[] = {
 #define PWM_NUMOF           ARRAY_SIZE(pwm_config)
 /** @} */
 
+/**
+ * @name    SPI configuration
+ * @{
+ */
+static const spi_conf_t spi_config[] = {
+    {
+        .dev  = NRF_SPIM1_S,
+        .sclk = GPIO_PIN(0, 17),
+        .mosi = GPIO_PIN(0, 13),
+        .miso = GPIO_PIN(0, 14),
+    }
+};
+
+#define SPI_NUMOF           ARRAY_SIZE(spi_config)
+/** @} */
+
 #ifdef __cplusplus
 }
 #endif

boards/nrf9160dk/include/periph_conf.h

@@ -113,9 +113,6 @@ static const uart_conf_t uart_config[] = {
     },
 };
 
-#define UART_0_ISR          (isr_uarte0_spim0_spis0_twim0_twis0) /**< UART0_IRQ */
-#define UART_1_ISR          (isr_uarte1_spim1_spis1_twim1_twis1) /**< UART1_IRQ */
-
 #define UART_NUMOF          ARRAY_SIZE(uart_config) /**< UART configuration NUMOF */
 /** @} */
 

cpu/atmega_common/atmega_cpu.c

@@ -2,7 +2,7 @@
  * Copyright (C) 2014 Freie Universität Berlin, Hinnerk van Bruinehsen
  *               2017 RWTH Aachen, Josua Arndt
  *               2018 Matthew Blue
- *               2021 Gerson Fernando Budke
+ *               2021-2023 Gerson Fernando Budke
  *               2023 Hugues Larrive
  *
  * This file is subject to the terms and conditions of the GNU Lesser
@@ -30,6 +30,7 @@
 
 #include "board.h"
 #include "cpu.h"
+#include "irq_arch.h"
 #include "panic.h"
 
 #define ENABLE_DEBUG 0
@@ -85,7 +86,7 @@ void __attribute__((weak)) avr8_clk_init(void)
  * EIFR – External Interrupt Flag Register
  * PCIFR – Pin Change Interrupt Flag Register
  */
-ISR(BADISR_vect)
+ISR(BADISR_vect, ISR_NAKED)
 {
     avr8_reset_cause();
 
@@ -109,10 +110,5 @@ ISR(BADISR_vect)
 }
 
 #if defined(BAT_LOW_vect)
-ISR(BAT_LOW_vect, ISR_BLOCK)
-{
-    avr8_enter_isr();
-    DEBUG("BAT_LOW\n");
-    avr8_exit_isr();
-}
+AVR8_ISR(BAT_LOW_vect, DEBUG, "BAT_LOW\n");
 #endif

cpu/atmega_common/periph/gpio.c

@@ -2,6 +2,8 @@
  * Copyright (C) 2015 HAW Hamburg
  *               2016 INRIA
  *               2023 Hugues Larrive
+ *               2023 Gerson Fernando Budke
+
  *
  * This file is subject to the terms and conditions of the GNU Lesser
  * General Public License v2.1. See the file LICENSE in the top level
@@ -23,6 +25,7 @@
  * @author      Torben Petersen <petersen@ibr.cs.tu-bs.de>
  * @author      Marian Buschsieweke <marian.buschsieweke@ovgu.de>
  * @author      Hugues Larrive <hugues.larrive@pm.me>
+ * @author      Gerson Fernando Budke <nandojve@gmail.com>
  *
  * @}
  */
@@ -32,6 +35,7 @@
 #include <avr/interrupt.h>
 
 #include "cpu.h"
+#include "irq.h"
 #include "board.h"
 #include "periph/gpio.h"
 #include "periph_conf.h"
@@ -368,16 +372,13 @@ void gpio_irq_disable(gpio_t pin)
 
 static inline void irq_handler(uint8_t int_num)
 {
-    avr8_enter_isr();
     config[int_num].cb(config[int_num].arg);
-    avr8_exit_isr();
 }
 
 #ifdef ENABLE_PCINT
 /* inline function that is used by the PCINT ISR */
 static inline void pcint_handler(uint8_t bank, uint8_t enabled_pcints)
 {
-    avr8_enter_isr();
     /* Find right item */
     uint8_t idx = 0;
 
@@ -406,89 +407,50 @@ static inline void pcint_handler(uint8_t bank, uint8_t enabled_pcints)
         enabled_pcints = enabled_pcints >> 1;
         idx++;
     }
-
-    avr8_exit_isr();
 }
 #ifdef MODULE_ATMEGA_PCINT0
-ISR(PCINT0_vect, ISR_BLOCK)
-{
-    pcint_handler(PCINT0_IDX, PCMSK0);
-}
+AVR8_ISR(PCINT0_vect, pcint_handler, PCINT0_IDX, PCMSK0);
 #endif /* MODULE_ATMEGA_PCINT0 */
 
 #ifdef MODULE_ATMEGA_PCINT1
-ISR(PCINT1_vect, ISR_BLOCK)
-{
-    pcint_handler(PCINT1_IDX, PCMSK1);
-}
+AVR8_ISR(PCINT1_vect, pcint_handler, PCINT1_IDX, PCMSK1);
 #endif  /* MODULE_ATMEGA_PCINT1 */
 
 #ifdef MODULE_ATMEGA_PCINT2
-ISR(PCINT2_vect, ISR_BLOCK)
-{
-    pcint_handler(PCINT2_IDX, PCMSK2);
-}
+AVR8_ISR(PCINT2_vect, pcint_handler, PCINT2_IDX, PCMSK2);
 #endif  /* MODULE_ATMEGA_PCINT2 */
 
 #ifdef MODULE_ATMEGA_PCINT3
-ISR(PCINT3_vect, ISR_BLOCK)
-{
-    pcint_handler(PCINT3_IDX, PCMSK3);
-}
+AVR8_ISR(PCINT3_vect, pcint_handler, PCINT3_IDX, PCMSK3);
 #endif  /* MODULE_ATMEGA_PCINT3 */
 
 #endif  /* ENABLE_PCINT */
 
-ISR(INT0_vect, ISR_BLOCK)
-{
-    irq_handler(0); /**< predefined interrupt pin */
-}
-
-ISR(INT1_vect, ISR_BLOCK)
-{
-    irq_handler(1); /**< predefined interrupt pin */
-}
+AVR8_ISR(INT0_vect, irq_handler, 0); /**< predefined interrupt pin */
+AVR8_ISR(INT1_vect, irq_handler, 1); /**< predefined interrupt pin */
 
 #if defined(INT2_vect)
-ISR(INT2_vect, ISR_BLOCK)
-{
-    irq_handler(2); /**< predefined interrupt pin */
-}
+AVR8_ISR(INT2_vect, irq_handler, 2); /**< predefined interrupt pin */
 #endif
 
 #if defined(INT3_vect)
-ISR(INT3_vect, ISR_BLOCK)
-{
-    irq_handler(3); /**< predefined interrupt pin */
-}
+AVR8_ISR(INT3_vect, irq_handler, 3); /**< predefined interrupt pin */
 #endif
 
 #if defined(INT4_vect)
-ISR(INT4_vect, ISR_BLOCK)
-{
-    irq_handler(4); /**< predefined interrupt pin */
-}
+AVR8_ISR(INT4_vect, irq_handler, 4); /**< predefined interrupt pin */
 #endif
 
 #if defined(INT5_vect)
-ISR(INT5_vect, ISR_BLOCK)
-{
-    irq_handler(5); /**< predefined interrupt pin */
-}
+AVR8_ISR(INT5_vect, irq_handler, 5); /**< predefined interrupt pin */
 #endif
 
 #if defined(INT6_vect)
-ISR(INT6_vect, ISR_BLOCK)
-{
-    irq_handler(6); /**< predefined interrupt pin */
-}
+AVR8_ISR(INT6_vect, irq_handler, 6); /**< predefined interrupt pin */
 #endif
 
 #if defined(INT7_vect)
-ISR(INT7_vect, ISR_BLOCK)
-{
-    irq_handler(7); /**< predefined interrupt pin */
-}
+AVR8_ISR(INT7_vect, irq_handler, 7); /**< predefined interrupt pin */
 #endif
 
 #endif /* MODULE_PERIPH_GPIO_IRQ */