fix timer skew for slow clocks

use SAM0_GCLK_TIMER instead of SAM0_GCLK_8MHZ in boards config
RIOT-OS · May 5, 2021 · 2b213b2 · 2b213b2
1 parent 43103a6
commit 2b213b2
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Showing 7 changed files with 15 additions and 11 deletions.
diff --git a/boards/bastwan/include/periph_conf.h b/boards/bastwan/include/periph_conf.h
@@ -48,7 +48,7 @@ static const tc32_conf_t timer_config[] = {
         .mclk = &MCLK->APBCMASK.reg,
         .mclk_mask = MCLK_APBCMASK_TC0 | MCLK_APBCMASK_TC1,
         .gclk_id = TC0_GCLK_ID,
-        .gclk_src = SAM0_GCLK_8MHZ,
+        .gclk_src = SAM0_GCLK_TIMER,
         .flags = TC_CTRLA_MODE_COUNT32,
     }
 };

diff --git a/boards/saml21-xpro/include/periph_conf.h b/boards/saml21-xpro/include/periph_conf.h
@@ -51,7 +51,7 @@ static const tc32_conf_t timer_config[] = {
         .mclk           = &MCLK->APBCMASK.reg,
         .mclk_mask      = MCLK_APBCMASK_TC0 | MCLK_APBCMASK_TC1,
         .gclk_id        = TC0_GCLK_ID,
-        .gclk_src       = SAM0_GCLK_8MHZ,
+        .gclk_src       = SAM0_GCLK_TIMER,
         .flags          = TC_CTRLA_MODE_COUNT32,
     }
 };
@@ -124,7 +124,7 @@ static const pwm_conf_t pwm_config[] = {
     { .tim  = TCC_CONFIG(TCC0),
       .chan = pwm_chan0_config,
       .chan_numof = ARRAY_SIZE(pwm_chan0_config),
-      .gclk_src = SAM0_GCLK_8MHZ,
+      .gclk_src = SAM0_GCLK_TIMER,
     },
 #endif
 };
@@ -222,7 +222,7 @@ static const adc_conf_chan_t adc_channels[] = {
  * @{
  */
                             /* Must not exceed 12 MHz */
-#define DAC_CLOCK           SAM0_GCLK_8MHZ
+#define DAC_CLOCK           SAM0_GCLK_TIMER
                             /* use Vcc as reference voltage */
 #define DAC_VREF            DAC_CTRLB_REFSEL_VDDANA
 /** @} */

diff --git a/boards/samr30-xpro/include/periph_conf.h b/boards/samr30-xpro/include/periph_conf.h
@@ -41,7 +41,7 @@ static const tc32_conf_t timer_config[] = {
         .mclk           = &MCLK->APBCMASK.reg,
         .mclk_mask      = MCLK_APBCMASK_TC0 | MCLK_APBCMASK_TC1,
         .gclk_id        = TC0_GCLK_ID,
-        .gclk_src       = SAM0_GCLK_8MHZ,
+        .gclk_src       = SAM0_GCLK_TIMER,
         .flags          = TC_CTRLA_MODE_COUNT32,
     }
 };

diff --git a/boards/samr34-xpro/include/periph_conf.h b/boards/samr34-xpro/include/periph_conf.h
@@ -48,7 +48,7 @@ static const tc32_conf_t timer_config[] = {
         .mclk           = &MCLK->APBCMASK.reg,
         .mclk_mask      = MCLK_APBCMASK_TC0 | MCLK_APBCMASK_TC1,
         .gclk_id        = TC0_GCLK_ID,
-        .gclk_src       = SAM0_GCLK_8MHZ,
+        .gclk_src       = SAM0_GCLK_TIMER,
         .flags          = TC_CTRLA_MODE_COUNT32,
     }
 };

diff --git a/boards/yarm/include/periph_conf.h b/boards/yarm/include/periph_conf.h
@@ -48,7 +48,7 @@ static const tc32_conf_t timer_config[] = {
         .mclk           = &MCLK->APBCMASK.reg,
         .mclk_mask      = MCLK_APBCMASK_TC0 | MCLK_APBCMASK_TC1,
         .gclk_id        = TC0_GCLK_ID,
-        .gclk_src       = SAM0_GCLK_8MHZ,
+        .gclk_src       = SAM0_GCLK_TIMER,
         .flags          = TC_CTRLA_MODE_COUNT32,
     }
 };

diff --git a/cpu/saml21/cpu.c b/cpu/saml21/cpu.c
@@ -99,8 +99,12 @@ uint32_t sam0_gclk_freq(uint8_t id)
     switch (id) {
     case SAM0_GCLK_MAIN:
         return CLOCK_CORECLOCK;
-    case SAM0_GCLK_8MHZ:
+    case SAM0_GCLK_TIMER:
+#if (CLOCK_CORECLOCK == 48000000U) || (CLOCK_CORECLOCK == 16000000U) || (CLOCK_CORECLOCK == 8000000U)
         return 8000000;
+#else
+        return 4000000;
+#endif
     case SAM0_GCLK_32KHZ:
         return 32768;
     case SAM0_GCLK_48MHZ:
@@ -292,8 +296,8 @@ void cpu_init(void)
         }
     }
     /* clock used by timers */
-    _gclk_setup(SAM0_GCLK_8MHZ, GCLK_GENCTRL_GENEN | GCLK_GENCTRL_SRC_OSC16M
-                | GCLK_GENCTRL_DIV(2));
+    _gclk_setup(SAM0_GCLK_TIMER, GCLK_GENCTRL_GENEN | GCLK_GENCTRL_SRC_OSC16M
+                | GCLK_GENCTRL_DIV(CLOCK_CORECLOCK/sam0_gclk_freq(SAM0_GCLK_TIMER)));
 
 #ifdef MODULE_PERIPH_PM
     PM->CTRLA.reg = PM_CTRLA_MASK & (~PM_CTRLA_IORET);

diff --git a/cpu/saml21/include/periph_cpu.h b/cpu/saml21/include/periph_cpu.h
@@ -44,7 +44,7 @@ extern "C" {
  */
 enum {
     SAM0_GCLK_MAIN  = 0,                 /**< Main clock */
-    SAM0_GCLK_8MHZ  = 1,                 /**< 8MHz clock */
+    SAM0_GCLK_TIMER = 1,                 /**< 4/8MHz clock for timers */
     SAM0_GCLK_32KHZ = 2,                 /**< 32 kHz clock */
     SAM0_GCLK_48MHZ = 3,                 /**< 48MHz clock */
 };