Merge #18056 #19571 #19589

18056: pkg/cmsis: use unique package for CMSIS headers, DSP and NN modules r=benpicco a=aabadie



19571: cpu/stm32/periph_adc: fixes and improvements for L4 support r=benpicco a=gschorcht

### Contribution description

This PR provides the following fixes and improvements for the `periph_adc` implementation for STM32L4.
- Support STM32L496AG added.
- Instead of defining the number of ADC devices for each MCU model, the number of ADC devices is determined from ADCx definitions in CMSIS header.
- MCU specific register/value defines are valid for all L4 MCUs, model based conditional compilation is removed.
- The ADC clock disable function is fixed using a counter. The counter is incremented in `prep` and decremented in `done`. The ADC clock is disabled if the counter becomes 0.
- For boards that have not connected the V_REF+ pin to an external reference voltage, the VREFBUF peripheral can be used as V_REF+ (if supported) by setting `VREFBUF_ENABLE=1`.
- The ASCR register is available and has to be set for all STM32L471xx, STM32L475xx, STM32L476xx, STM32L485xx and STM32L486xx MCUs. Instead of using the CPU model for conditional compilation, the CPU line is used to support all MCU of that lines.
- Setting of SQR1 is fixed. Setting the SQR1 did only work before because the `ADC_SRQ_L` is set to 0 for a sequence length of 1.
- Setting the `ADC_CCR_CKMODE` did only work for the reset state. It is now cleared before it is set. Instead of using the `ADC_CCR_CKMODE_x` bits to set the mode, the mode defines are used.
 - Support for V_REFINT as ADC channel added.

### Testing procedure



19589: gnrc/gnrc_netif_hdr_print: printout timestamp if enabled r=aabadie a=chudov



Co-authored-by: Alexandre Abadie <alexandre.abadie@inria.fr>
Co-authored-by: Gunar Schorcht <gunar@schorcht.net>
Co-authored-by: chudov <chudov@gmail.com>

cpu/cortexm_common/Kconfig

@@ -11,6 +11,7 @@ config MODULE_CORTEXM_COMMON
     imply MODULE_NEWLIB_NANO
     select MODULE_PERIPH
     select MODULE_MALLOC_THREAD_SAFE if TEST_KCONFIG
+    select PACKAGE_CMSIS if TEST_KCONFIG
     help
         Common code for Cortex-M cores.
 

cpu/cortexm_common/Makefile.dep

@@ -26,3 +26,6 @@ endif
 
 # Make calls to malloc and friends thread-safe
 USEMODULE += malloc_thread_safe
+
+# CMSIS headers are fetched using a package
+USEPKG += cmsis

cpu/cortexm_common/Makefile.include

@@ -1,6 +1,5 @@
 # include module specific includes
 INCLUDES += -I$(RIOTCPU)/cortexm_common/include
-INCLUDES += -I$(RIOTCPU)/cortexm_common/include/vendor
 
 # All variables must be defined in the CPU configuration when using the common
 # `ldscripts/cortexm.ld`