fixup! cpu: Add atomic_utils impl for CortexM CPUs

RIOT-OS · Jul 14, 2020 · 7a903e9 · 7a903e9
1 parent cc2bffc
commit 7a903e9
Showing 1 changed file with 29 additions and 34 deletions.
diff --git a/cpu/cortexm_common/include/atomic_utils_arch.h b/cpu/cortexm_common/include/atomic_utils_arch.h
@@ -19,6 +19,9 @@
 #ifndef ATOMIC_UTILS_CPU_H
 #define ATOMIC_UTILS_CPU_H
 
+#include "bit.h"
+#include "periph_cpu.h"
+
 #ifdef __cplusplus
 extern "C" {
 #endif
@@ -59,90 +62,82 @@ static inline void atomic_store_u32(uint32_t *dest, uint32_t val)
     __atomic_store_4(dest, val, __ATOMIC_SEQ_CST);
 }
 
-#if defined(CPU_CORE_CORTEX_M3) || defined(CPU_CORE_CORTEX_M4) || defined(CPU_CORE_CORTEX_M4)
+#if IS_ACTIVE(CPU_HAS_BITBAND)
 #define ATOMIC_BITMASK __attribute__((section(''.srambb'')))
 
-static inline volatile uint32_t *bitband_addr(void *maskaddr, uint8_t bit)
-{
-    static const uintptr_t bbalias = 0x22000000;
-    static const uintptr_t bbregion = 0x20000000
-    uintptr_t offset = ((((uintptr_t)maskaddr) - bbregion) << 5) + (bit << 2);
-    return (volatile uint32_t *)(bbalias + offset);
-}
-
 #define HAS_ATOMIC_SET_BIT_U8
 static inline void atomic_set_bit_u8(uint8_t *mask, uint8_t bit)
 {
-    __asm__ volatile (::: "memory");
+    __asm__ volatile ("" ::: "memory");
     volatile uint32_t *bbaddr = bitband_addr(mask, bit);
-    bbaddr = 1;
-    __asm__ volatile (::: "memory");
+    *bbaddr = 1;
+    __asm__ volatile ("" ::: "memory");
 }
 
 #define HAS_ATOMIC_SET_BIT_U16
 static inline void atomic_set_bit_u16(uint16_t *mask, uint8_t bit)
 {
-    __asm__ volatile (::: "memory");
+    __asm__ volatile ("" ::: "memory");
     volatile uint32_t *bbaddr = bitband_addr(mask, bit);
-    bbaddr = 1;
-    __asm__ volatile (::: "memory");
+    *bbaddr = 1;
+    __asm__ volatile ("" ::: "memory");
 }
 
 #define HAS_ATOMIC_SET_BIT_U32
 static inline void atomic_set_bit_u32(uint32_t *mask, uint8_t bit)
 {
-    __asm__ volatile (::: "memory");
+    __asm__ volatile ("" ::: "memory");
     volatile uint32_t *bbaddr = bitband_addr(mask, bit);
-    bbaddr = 1;
-    __asm__ volatile (::: "memory");
+    *bbaddr = 1;
+    __asm__ volatile ("" ::: "memory");
 }
 
 #define HAS_ATOMIC_SET_BIT_U64
 static inline void atomic_set_bit_u64(uint64_t *mask, uint8_t bit)
 {
-    __asm__ volatile (::: "memory");
+    __asm__ volatile ("" ::: "memory");
     volatile uint32_t *bbaddr = bitband_addr(mask, bit);
-    bbaddr = 1;
-    __asm__ volatile (::: "memory");
+    *bbaddr = 1;
+    __asm__ volatile ("" ::: "memory");
 }
 
 #define HAS_ATOMIC_CLEAR_BIT_U8
 static inline void atomic_clear_bit_u8(uint8_t *mask, uint8_t bit)
 {
-    __asm__ volatile (::: "memory");
+    __asm__ volatile ("" ::: "memory");
     volatile uint32_t *bbaddr = bitband_addr(mask, bit);
-    bbaddr = 0;
-    __asm__ volatile (::: "memory");
+    *bbaddr = 0;
+    __asm__ volatile ("" ::: "memory");
 }
 
 #define HAS_ATOMIC_CLEAR_BIT_U16
 static inline void atomic_clear_bit_u16(uint16_t *mask, uint8_t bit)
 {
-    __asm__ volatile (::: "memory");
+    __asm__ volatile ("" ::: "memory");
     volatile uint32_t *bbaddr = bitband_addr(mask, bit);
-    bbaddr = 0;
-    __asm__ volatile (::: "memory");
+    *bbaddr = 0;
+    __asm__ volatile ("" ::: "memory");
 }
 
 #define HAS_ATOMIC_CLEAR_BIT_U32
 static inline void atomic_clear_bit_u32(uint32_t *mask, uint8_t bit)
 {
-    __asm__ volatile (::: "memory");
+    __asm__ volatile ("" ::: "memory");
     volatile uint32_t *bbaddr = bitband_addr(mask, bit);
-    bbaddr = 0;
-    __asm__ volatile (::: "memory");
+    *bbaddr = 0;
+    __asm__ volatile ("" ::: "memory");
 }
 
 #define HAS_ATOMIC_CLEAR_BIT_U64
 static inline void atomic_clear_bit_u64(uint64_t *mask, uint8_t bit)
 {
-    __asm__ volatile (::: "memory");
+    __asm__ volatile ("" ::: "memory");
     volatile uint32_t *bbaddr = bitband_addr(mask, bit);
-    bbaddr = 0;
-    __asm__ volatile (::: "memory");
+    *bbaddr = 0;
+    __asm__ volatile ("" ::: "memory");
 }
 
-#endif /* Cortex-M3 || Cortex-M4 || Cortex-M4F */
+#endif /* CPU_HAS_BITBAND */
 
 #ifdef __cplusplus
 }