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boards/hip-badge: add HiP Badge board definition #19076
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Could you imagine to split off the |
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cpu/esp32/include/irq_arch.h
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@@ -50,6 +50,7 @@ extern "C" { | |||
#define CPU_INUM_SYSTIMER 20 /**< Level interrupt with medium priority 2 */ | |||
#define CPU_INUM_BLE 21 /**< Level interrupt with medium priority 2 */ | |||
#define CPU_INUM_CACHEERR 25 /**< Level interrupt with high priority 4 */ | |||
#define CPU_INUM_SERIAL_JTAG 26 /**< Level interrupt with low priority 1 */ |
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Please align the indent of the interrupt values.
cpu/esp32/include/irq_arch.h
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@@ -50,6 +50,7 @@ extern "C" { | |||
#define CPU_INUM_SYSTIMER 20 /**< Level interrupt with medium priority 2 */ | |||
#define CPU_INUM_BLE 21 /**< Level interrupt with medium priority 2 */ | |||
#define CPU_INUM_CACHEERR 25 /**< Level interrupt with high priority 4 */ | |||
#define CPU_INUM_SERIAL_JTAG 26 /**< Level interrupt with low priority 1 */ |
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The level specifies the priority of the the interrupts which is flexible for RISC-V based ESP32x SoCs but fixed for Xtensa-based SoCs. The value given here is the fixed value as used by the Xtensa-based SoCs which is 5.
#define CPU_INUM_SERIAL_JTAG 26 /**< Level interrupt with low priority 1 */ | |
#define CPU_INUM_SERIAL_JTAG 26 /**< Level interrupt with high priority 5 */ |
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We should check whether we could use another interrupt because level 5 is the highest one and higher than the cache error or WDT interrupts which have a level of 4.
If I'm not wrong, level 1 interrupt 10 should be free.
@@ -83,6 +83,9 @@ static const struct intr_handle_data_t _irq_data_table[] = { | |||
#if defined(CPU_FAM_ESP32S2) || defined(CPU_FAM_ESP32S3) | |||
{ ETS_USB_INTR_SOURCE, CPU_INUM_USB, 1 }, | |||
#endif | |||
#if defined(CPU_INUM_SERIAL_JTAG) | |||
{ ETS_USB_SERIAL_JTAG_INTR_SOURCE, CPU_INUM_SERIAL_JTAG, 1 }, |
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{ ETS_USB_SERIAL_JTAG_INTR_SOURCE, CPU_INUM_SERIAL_JTAG, 1 }, | |
{ ETS_USB_SERIAL_JTAG_INTR_SOURCE, CPU_INUM_SERIAL_JTAG, 5 }, |
See my comment above.
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Hm with that, stdio is no longer working.
The highest I can set it to is 3
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This is wrong again. Either the level is defined to be 5 if CPU_INUM_SERIAL_JTAG=26
is used or CPU_INUM_SERIAL_JTAG
is set to 10 and then the level has to be be 1. The mapping of interrupt numbers and priorities is hardwired in Xtensa cores and can't be set by software.
My concern is that level 5 is much too high because it is higher than cache error exception and WDTs. Therefore, I suggested to use interrupt 10 with level 1.
The whole mapping, I found in past in any former ESP-IDF version in `espressif/soc/soc.hext ended by a column with RIOT usage:
/**************************************************************************
* Int Level Type PRO CPU usage APP CPU uasge RIOT Comment
* 0 1 extern level WMAC Reserved - wDev_ProcessFiq
* 1 1 extern level BT/BLE Host HCI DMA BT/BLE Host HCI DMA
* 2 1 extern level GPIO
* 3 1 extern level CAN
* 4 1 extern level WBB UART
* 5 1 extern level BT/BLE Controller BT/BLE Controller -
* 6 1 timer FreeRTOS Tick(L1) FreeRTOS Tick(L1) - CCOMPARE0
* 7 1 software BT/BLE VHCI BT/BLE VHCI -
* 8 1 extern level BT/BLE BB(RX/TX) BT/BLE BB(RX/TX) USB
* 9 1 extern level RTC
* 10 1 extern edge
* 11 3 profiling
* 12 1 extern level I2C
* 13 1 extern level WDT
* 14 7 nmi Reserved Reserved
* 15 3 timer FreeRTOS Tick(L3) FreeRTOS Tick(L3) - CCOMPARE1
* 16 5 timer - CCOMPARE2
* 17 1 extern level thread_yield_higher
* 18 1 extern level ETH
* 19 2 extern level TIMER
* 20 2 extern level FRC2 ESP-IDF FRC2 legacy
* 21 2 extern level BLE
* 22 3 extern edge
* 23 3 extern level
* 24 4 extern level TG1_WDT
* 25 4 extern level CACHEERR
* 26 5 extern level
* 27 3 extern level Reserved Reserved
* 28 4 extern edge DPORT ACCESS DPORT ACCESS Not in single core
* 29 3 software Reserved Reserved
* 30 4 extern edge Reserved Reserved
* 31 5 extern level
**************************************************************************
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hm I think I want a level triggered IRQ for stdout though
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Does it finally matter?
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It doesn't make a difference on the ESP32-C3.
But there the level is configurable, so maybe software already does configure it to be a level interrupt?
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I think it is time to implement the dynamic interrupt allocation as ESP-IDF intr_alloc
function does where the application just specify requirements like edge/level, priority, ... and the intr_alloc
function assigns the next free interrupt that satisfies the reuirements.
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I'm not really sure whether all the BT/BLE interrupts are really used. It would be helpful to record a trace which interrupts by the ESP-IDF and the WiFi/BLE libraries are really allocated.
I wonder if it would make sense, to call the board directory Please add a |
@@ -10,6 +10,7 @@ STDIO_MODULES = \ | |||
stdio_uart \ | |||
stdio_telnet \ | |||
stdio_tinyusb_cdc_acm \ | |||
stdio_usb_serial_jtag \ |
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The same here?
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No, this is just a list of all possible stdio modules to select stdio_uart
if none of them is selected.
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... required for the decision whether to enable stdio_acd_acm
.
At the back there is J1 which should be something like a connector for the antenna according to the schematic. |
Build failed: |
Ah, I forgot, the board needs a Kconfig file.
😉 |
Let's see if this does the job bors try |
tryBuild failed: |
This still needs squashing |
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bors retry |
Note that the last |
There is the added Kconfig, but if that is OK we can directly do a bors merge |
tryBuild failed: |
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Ok, the naming of bors retry |
bors merge |
Build failed: |
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bors merge |
Build succeeded: |
Thank you for the quick review! |
Contribution description
This adds support for the HiP Badge.
What works:
IrDA (configured on UART1, untested)IR transceiver circuit on the board is brokenSGP30 air quality sensornot populatedMAX17048 fuel gaugenot populatedSPI (is it even connected / exposed?)not usedWiFi / ESP Now (not board specific)board has no antenna!BLE (same as WiFi)examples/nimble_scanner
andexamples/nimble_heart_rate_sensor
works regardless of the missing antenna (PCB trace to unpopulated antenna only)Testing procedure
Install the esp32c3 toolchain:
Flash any test / application
If stdio does not work, just reset the board by pressing the blue reset button (SW3).
For a yet unknown reason I don't get any TX empty interrupts right after flashing / soft reboot, but it works after a reset.
Issues/PRs references
requires #19096 for stdio to work with any application that uses the radio