cpu/nrf53: add I2C and SPI support

boards/nrf5340dk-app/Kconfig

@@ -11,11 +11,15 @@ config BOARD_NRF5340DK_APP
     bool
     default y
     select CPU_MODEL_NRF5340_APP
+    select HAS_PERIPH_I2C
+    select HAS_PERIPH_SPI
+    select HAS_PERIPH_SPI_GPIO_MODE
     select HAS_PERIPH_PWM
     select HAS_PERIPH_RTT
     select HAS_PERIPH_TIMER
     select HAS_PERIPH_UART
     select HAS_PERIPH_UART_HW_FC
     select HAS_PERIPH_USBDEV
+    select HAVE_MTD_SPI_NOR
 
     # Put other features for this board (in alphabetical order)

boards/nrf5340dk-app/Makefile.dep

@@ -0,0 +1,9 @@
+ifneq (,$(filter mtd,$(USEMODULE)))
+  USEMODULE += mtd_spi_nor
+endif
+
+# default to using littlefs2 on the external flash
+ifneq (,$(filter vfs_default,$(USEMODULE)))
+  USEPKG += littlefs2
+  USEMODULE += mtd
+endif

boards/nrf5340dk-app/Makefile.features

@@ -2,8 +2,10 @@ CPU_MODEL = nrf5340_app
 CPU = nrf53
 
 # Put defined MCU peripherals here (in alphabetical order)
+FEATURES_PROVIDED += periph_i2c
 FEATURES_PROVIDED += periph_pwm
 FEATURES_PROVIDED += periph_rtt
+FEATURES_PROVIDED += periph_spi
 FEATURES_PROVIDED += periph_timer
 FEATURES_PROVIDED += periph_uart
 FEATURES_PROVIDED += periph_uart_hw_fc

boards/nrf5340dk-app/board.c

@@ -0,0 +1,58 @@
+/*
+ * Copyright (C) 2023 Mesotic SAS
+ *
+ * This file is subject to the terms and conditions of the GNU Lesser
+ * General Public License v2.1. See the file LICENSE in the top level
+ * directory for more details.
+ */
+
+/**
+ * @ingroup     boards_nrf5340dk-app
+ * @{
+ *
+ * @file
+ * @brief       Board specific implementations for the Nordic nRF5340DK board
+ *
+ * @author      Dylan Laduranty <dylan.laduranty@mesotic.com>
+ * @}
+ */
+
+#include "board.h"
+#include "periph/gpio.h"
+#include "timex.h"
+#ifdef MODULE_VFS_DEFAULT
+#include "vfs_default.h"
+#endif
+
+#ifdef MODULE_MTD_SPI_NOR
+#include "mtd_spi_nor.h"
+/* MX25R64 */
+static const mtd_spi_nor_params_t _nrf5340_nor_params = {
+    .opcode = &mtd_spi_nor_opcode_default,
+    .wait_chip_erase = 240 * US_PER_SEC,
+    .wait_64k_erase = 800 * US_PER_MS,
+    .wait_sector_erase = 240 * US_PER_MS,
+    .wait_chip_wake_up = 1 * US_PER_MS,
+    .clk  = MHZ(54),
+    .flag = SPI_NOR_F_SECT_4K | SPI_NOR_F_SECT_64K,
+    .spi  = SPI_DEV(0),
+    .mode = SPI_MODE_0,
+    .cs   = BOARD_QSPI_PIN_CS,
+    .wp   = BOARD_QSPI_PIN_WP,
+    .hold = BOARD_QSPI_PIN_HOLD,
+};
+
+static mtd_spi_nor_t nrf5340_nor_dev = {
+    .base = {
+        .driver = &mtd_spi_nor_driver,
+        .page_size = 256,
+        .pages_per_sector = 16,
+    },
+    .params = &_nrf5340_nor_params,
+};
+mtd_dev_t *mtd0 = (mtd_dev_t *)&nrf5340_nor_dev;
+
+#ifdef MODULE_VFS_DEFAULT
+VFS_AUTO_MOUNT(littlefs2, VFS_MTD(nrf5340_nor_dev), VFS_DEFAULT_NVM(0), 0);
+#endif
+#endif /* MODULE_MTD_SPI_NOR */

boards/nrf5340dk-app/include/board.h

@@ -20,6 +20,7 @@
 #define BOARD_H
 
 #include "cpu.h"
+#include "mtd.h"
 
 #ifdef __cplusplus
 extern "C" {
@@ -95,6 +96,19 @@ extern "C" {
 #define BTN3_MODE           GPIO_IN_PU       /**< BTN3 default mode */
 /** @} */
 
+/**
+ * @name MTD configuration
+ * @{
+ */
+extern mtd_dev_t *mtd0;
+#define MTD_0       mtd0
+#define MTD_NUMOF   1
+
+#define BOARD_QSPI_PIN_CS       GPIO_PIN(0, 18)     /**< SPI Flash Chip Select */
+#define BOARD_QSPI_PIN_WP       GPIO_PIN(0, 15)     /**< SPI Flash Write Protect */
+#define BOARD_QSPI_PIN_HOLD     GPIO_PIN(0, 16)     /**< SPI Flash Hold pin */
+/** @} */
+
 #ifdef __cplusplus
 }
 #endif

boards/nrf5340dk-app/include/periph_conf.h

@@ -70,8 +70,6 @@ static const uart_conf_t uart_config[] = {
     },
 };
 
-#define UART_0_ISR          (isr_serial0) /**< SERIAL0_IRQn */
-
 #define UART_NUMOF          ARRAY_SIZE(uart_config) /**< UART configuration NUMOF */
 /** @} */
 
@@ -112,6 +110,37 @@ static const pwm_conf_t pwm_config[] = {
 #define PWM_NUMOF           ARRAY_SIZE(pwm_config)
 /** @} */
 
+/**
+ * @name    SPI configuration
+ * @{
+ */
+static const spi_conf_t spi_config[] = {
+    {
+        .dev  = NRF_SPIM1_S,
+        .sclk = GPIO_PIN(0, 17),
+        .mosi = GPIO_PIN(0, 13),
+        .miso = GPIO_PIN(0, 14),
+    }
+};
+
+#define SPI_NUMOF           ARRAY_SIZE(spi_config)
+/** @} */
+
+/**
+ *  * @name    I2C configuration
+ *   * @{
+ *    */
+static const i2c_conf_t i2c_config[] = {
+    {
+        .dev = NRF_TWIM2_S,
+        .scl = GPIO_PIN(1, 3),
+        .sda = GPIO_PIN(1, 2),
+        .speed = I2C_SPEED_NORMAL
+    }
+};
+#define I2C_NUMOF           ARRAY_SIZE(i2c_config)
+/** @} */
+
 #ifdef __cplusplus
 }
 #endif

boards/nrf9160dk/include/periph_conf.h

@@ -113,9 +113,6 @@ static const uart_conf_t uart_config[] = {
     },
 };
 
-#define UART_0_ISR          (isr_uarte0_spim0_spis0_twim0_twis0) /**< UART0_IRQ */
-#define UART_1_ISR          (isr_uarte1_spim1_spis1_twim1_twis1) /**< UART1_IRQ */
-
 #define UART_NUMOF          ARRAY_SIZE(uart_config) /**< UART configuration NUMOF */
 /** @} */
 

cpu/nrf52/include/periph_cpu.h

@@ -27,14 +27,6 @@
 extern "C" {
 #endif
 
-/**
- * @brief   Enable the workaround for the SPI single byte transmit errata (No.
- * 58 on the nrf52832)
- */
-#ifdef CPU_MODEL_NRF52832XXAA
-#define ERRATA_SPI_SINGLE_BYTE_WORKAROUND (1)
-#endif
-
 /**
  * @brief   System core clock speed, fixed to 64MHz for all NRF52x CPUs
  */
@@ -45,18 +37,6 @@ extern "C" {
  */
 #define PERIPH_CLOCK        (16000000U)
 
-/**
- * @brief   Redefine some peripheral names to unify them between nRF51 and 52
- * @{
- */
-#define SPI_SCKSEL          (dev(bus)->PSEL.SCK)
-#define SPI_MOSISEL         (dev(bus)->PSEL.MOSI)
-#define SPI_MISOSEL         (dev(bus)->PSEL.MISO)
-#ifdef CPU_MODEL_NRF52832XXAA
-#define UART_IRQN           (UARTE0_UART0_IRQn)
-#endif
-/** @} */
-
 /**
  * @brief   The nRF52 family of CPUs provides a fixed number of 9 ADC lines
  */
@@ -66,14 +46,6 @@ extern "C" {
 #define ADC_NUMOF           (9U)
 #endif
 
-/**
- * @brief   SPI temporary buffer size for storing const data in RAM before
- *          initiating DMA transfer
- */
-#ifndef CONFIG_SPI_MBUF_SIZE
-#define CONFIG_SPI_MBUF_SIZE    64
-#endif
-
 /**
  * @brief   nRF52 specific naming of ADC lines (for convenience)
  */
@@ -109,70 +81,13 @@ typedef enum {
 /** @} */
 #endif /* ndef DOXYGEN */
 
-#ifndef DOXYGEN
-/**
- * @brief   Override I2C speed settings
- * @{
- */
-#define HAVE_I2C_SPEED_T
-typedef enum {
-    I2C_SPEED_LOW       = 0xff,                         /**< not supported */
-    I2C_SPEED_NORMAL    = TWIM_FREQUENCY_FREQUENCY_K100,    /**< 100kbit/s */
-    I2C_SPEED_FAST      = TWIM_FREQUENCY_FREQUENCY_K400,    /**< 400kbit/s */
-    I2C_SPEED_FAST_PLUS = 0xfe,                         /**< not supported */
-    I2C_SPEED_HIGH      = 0xfd,                         /**< not supported */
-} i2c_speed_t;
-/** @} */
-#endif /* ndef DOXYGEN */
-
-/**
- * @brief   I2C (TWI) configuration options
- * @{
- */
-typedef struct {
-    NRF_TWIM_Type *dev;         /**< TWIM hardware device */
-    gpio_t scl;                 /**< SCL pin */
-    gpio_t sda;                 /**< SDA pin */
-    i2c_speed_t speed;          /**< Bus speed */
-} i2c_conf_t;
-/** @} */
-
-/**
- * @name   Use shared I2C functions
- * @{
- */
-#define PERIPH_I2C_NEED_READ_REG
-#define PERIPH_I2C_NEED_WRITE_REG
-/** @} */
-
-/**
- * @name    Define macros for sda and scl pin to be able to reinitialize them
- * @{
- */
-#define i2c_pin_sda(dev) i2c_config[dev].sda
-#define i2c_pin_scl(dev) i2c_config[dev].scl
-/** @} */
-
 /**
  * @brief   Size of the UART TX buffer for non-blocking mode.
  */
 #ifndef UART_TXBUF_SIZE
 #define UART_TXBUF_SIZE    (64)
 #endif
 
-/**
- * @brief  SPI configuration values
- */
-typedef struct {
-    NRF_SPIM_Type *dev; /**< SPI device used */
-    gpio_t sclk;        /**< CLK pin */
-    gpio_t mosi;        /**< MOSI pin */
-    gpio_t miso;        /**< MISO pin */
-#if ERRATA_SPI_SINGLE_BYTE_WORKAROUND
-    uint8_t ppi;        /**< PPI channel */
-#endif
-} spi_conf_t;
-
 /**
  * @brief Common SPI/I2C interrupt callback
  *

cpu/nrf52/periph/Kconfig

@@ -7,16 +7,6 @@
 
 if TEST_KCONFIG
 
-config MODULE_PERIPH_UART_NONBLOCKING
-    depends on HAS_PERIPH_UART_NONBLOCKING
-    depends on MODULE_PERIPH_UART
-    select MODULE_TSRB
-
-config MODULE_PERIPH_SPI
-    depends on HAS_PERIPH_SPI
-    select MODULE_PERIPH_GPIO_IRQ if CPU_MODEL_NRF52832XXAA && HAS_PERIPH_GPIO_IRQ
-    select MODULE_PERIPH_SPI_GPIO_MODE if MODULE_PERIPH_SPI && HAS_PERIPH_SPI_GPIO_MODE
-
 config MODULE_SAUL_NRF_VDDH
     bool "Internal Voltage Sensor"
     depends on HAS_PERIPH_ADC

cpu/nrf52/spi_twi_irq.c

@@ -57,7 +57,7 @@
 #define SPIM_COUNT 2
 #endif
 
-static spi_twi_irq_cb_t _irq[SPIM_COUNT];
+static shared_irq_cb_t _irq[SPIM_COUNT];
 static void *_irq_arg[SPIM_COUNT];
 
 static mutex_t _locks[SPIM_COUNT];
@@ -123,8 +123,8 @@ static const IRQn_Type _isr[] = {
 #endif /* CPU_MODEL_NRF52840XXAA */
 };
 
-void spi_twi_irq_register_spi(NRF_SPIM_Type *bus,
-                              spi_twi_irq_cb_t cb, void *arg)
+void shared_irq_register_spi(NRF_SPIM_Type *bus,
+                              shared_irq_cb_t cb, void *arg)
 {
     size_t num = _spi_dev2num(bus);
 
@@ -133,8 +133,8 @@ void spi_twi_irq_register_spi(NRF_SPIM_Type *bus,
     NVIC_EnableIRQ(_isr[num]);
 }
 
-void spi_twi_irq_register_i2c(NRF_TWIM_Type *bus,
-                              spi_twi_irq_cb_t cb, void *arg)
+void shared_irq_register_i2c(NRF_TWIM_Type *bus,
+                              shared_irq_cb_t cb, void *arg)
 {
     size_t num = _i2c_dev2num(bus);
 
@@ -145,7 +145,7 @@ void spi_twi_irq_register_i2c(NRF_TWIM_Type *bus,
 }
 
 void nrf5x_i2c_acquire(NRF_TWIM_Type *bus,
-                       spi_twi_irq_cb_t cb, void *arg)
+                       shared_irq_cb_t cb, void *arg)
 {
     size_t num = _i2c_dev2num(bus);
     mutex_lock(&_locks[num]);
@@ -154,7 +154,7 @@ void nrf5x_i2c_acquire(NRF_TWIM_Type *bus,
 }
 
 void nrf5x_spi_acquire(NRF_SPIM_Type *bus,
-                       spi_twi_irq_cb_t cb, void *arg)
+                       shared_irq_cb_t cb, void *arg)
 {
     size_t num = _spi_dev2num(bus);
     mutex_lock(&_locks[num]);

cpu/nrf53/Kconfig

@@ -19,6 +19,7 @@ config CPU_FAM_NRF53
     select HAS_PERIPH_UART_MODECFG
     select HAS_PERIPH_WDT
     select HAS_PERIPH_WDT_CB
+    select MODULE_NRF_SHARED_SERIAL_IRQ
 
 ## CPU Models
 config CPU_MODEL_NRF5340_APP

cpu/nrf53/Makefile.dep

@@ -1,4 +1,9 @@
 USEMODULE += nrf53_vectors
+USEMODULE += nrf_shared_serial_irq
+
+ifneq (,$(filter periph_spi,$(USEMODULE)))
+  USEMODULE += periph_spi_gpio_mode
+endif
 
 include $(RIOTCPU)/nrf5x_common/Makefile.dep
 include $(RIOTCPU)/cortexm_common/Makefile.dep

cpu/nrf53/Makefile.features

@@ -1,4 +1,6 @@
 CPU_CORE = cortex-m33
 CPU_FAM  = nrf53
 
+FEATURES_PROVIDED += periph_spi_gpio_mode
+
 include $(RIOTCPU)/nrf5x_common/Makefile.features