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cpu/stm32: remove redundant conditional compile block #20495

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merged 2 commits into from
Mar 22, 2024
Merged

cpu/stm32: remove redundant conditional compile block #20495

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fd105b7
cpu/stm32: remove redundant conditional compile
Enoch247 Mar 20, 2024
1e45261
cpu/stm32: moved includes out of header where not used
Enoch247 Mar 20, 2024
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4 changes: 4 additions & 0 deletions cpu/stm32/include/clk/c0/cfg_clock_default.h
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Expand Up @@ -19,6 +19,10 @@
#ifndef CLK_C0_CFG_CLOCK_DEFAULT_H
#define CLK_C0_CFG_CLOCK_DEFAULT_H

#include "cfg_clock_common_fx_gx_mp1_c0.h"
#include "kernel_defines.h"
#include "macros/units.h"

#ifdef __cplusplus
extern "C" {
#endif
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2 changes: 2 additions & 0 deletions cpu/stm32/include/clk/cfg_clock_common_fx_gx_mp1_c0.h
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Expand Up @@ -23,6 +23,8 @@
#ifndef CLK_CFG_CLOCK_COMMON_FX_GX_MP1_C0_H
#define CLK_CFG_CLOCK_COMMON_FX_GX_MP1_C0_H

#include "kernel_defines.h"

#ifdef __cplusplus
extern "C" {
#endif
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2 changes: 2 additions & 0 deletions cpu/stm32/include/clk/cfg_clock_common_lx_u5_wx.h
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Expand Up @@ -23,6 +23,8 @@
#ifndef CLK_CFG_CLOCK_COMMON_LX_U5_WX_H
#define CLK_CFG_CLOCK_COMMON_LX_U5_WX_H

#include "kernel_defines.h"

#ifdef __cplusplus
extern "C" {
#endif
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14 changes: 0 additions & 14 deletions cpu/stm32/include/clk/clk_conf.h
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Expand Up @@ -19,20 +19,6 @@
#ifndef CLK_CLK_CONF_H
#define CLK_CLK_CONF_H

#include "kernel_defines.h"
#include "macros/units.h"

#if defined(CPU_FAM_STM32F0) || defined(CPU_FAM_STM32F1) || \
defined(CPU_FAM_STM32F2) || defined(CPU_FAM_STM32F3) || \
defined(CPU_FAM_STM32F4) || defined(CPU_FAM_STM32F7) || \
defined(CPU_FAM_STM32G0) || defined(CPU_FAM_STM32G4) || \
defined(CPU_FAM_STM32MP1) || defined(CPU_FAM_STM32C0)
#include "cfg_clock_common_fx_gx_mp1_c0.h"
#else /* CPU_FAM_STM32L0 || CPU_FAM_STM32L1 || CPU_FAM_STM32L4 ||
* CPU_FAM_STM32L5 || CPU_FAM_STM32U5 || CPU_FAM_STM32WB */
#include "cfg_clock_common_lx_u5_wx.h"
#endif

#if defined(CPU_FAM_STM32F0) || defined(CPU_FAM_STM32F1) || \
defined(CPU_FAM_STM32F3)
#include "f0f1f3/cfg_clock_default.h"
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4 changes: 4 additions & 0 deletions cpu/stm32/include/clk/f0f1f3/cfg_clock_default.h
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Expand Up @@ -26,6 +26,10 @@
#ifndef CLK_F0F1F3_CFG_CLOCK_DEFAULT_H
#define CLK_F0F1F3_CFG_CLOCK_DEFAULT_H

#include "cfg_clock_common_fx_gx_mp1_c0.h"
#include "kernel_defines.h"
#include "macros/units.h"
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#ifdef __cplusplus
extern "C" {
#endif
Expand Down Expand Up @@ -102,7 +106,7 @@
* PLL_MUL: multiplier, allowed range: [2:16]
* CORECLOCK -> 48MHz Max on F0, 72MHz MAX on F1/F3!
*/
#define CLOCK_CORECLOCK ((CLOCK_PLL_SRC / CONFIG_CLOCK_PLL_PREDIV) * CONFIG_CLOCK_PLL_MUL)

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#ifdef CPU_FAM_STM32F0
#if CLOCK_CORECLOCK > MHZ(48)
#error "SYSCLK cannot exceed 48MHz"
Expand All @@ -123,7 +127,7 @@
#define CONFIG_CLOCK_APB1_DIV (2)
#endif
#endif
#define CLOCK_APB1 (CLOCK_AHB / CONFIG_CLOCK_APB1_DIV) /* PCLK1, max: 48MHz (F0), 36MHz (F1/F3)*/

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#ifdef CPU_FAM_STM32F0
/* APB2 and APB1 are the same bus but configuration registers still follows the
* split between APB1 and APB2. Since it's the same bus, APB2 clock is equal to APB1 clock.
Expand All @@ -133,7 +137,7 @@
#ifndef CONFIG_CLOCK_APB2_DIV
#define CONFIG_CLOCK_APB2_DIV (1)
#endif
#define CLOCK_APB2 (CLOCK_AHB / CONFIG_CLOCK_APB2_DIV) /* PCLK2, max: 72MHz */

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#endif
/** @} */

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3 changes: 3 additions & 0 deletions cpu/stm32/include/clk/f2f4f7/cfg_clock_default.h
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Expand Up @@ -19,6 +19,9 @@
#ifndef CLK_F2F4F7_CFG_CLOCK_DEFAULT_H
#define CLK_F2F4F7_CFG_CLOCK_DEFAULT_H

#include "cfg_clock_common_fx_gx_mp1_c0.h"
#include "kernel_defines.h"

#if defined(CPU_FAM_STM32F2)
#include "f2f4f7/cfg_clock_default_120.h"
#elif defined(CPU_FAM_STM32F4)
Expand Down Expand Up @@ -66,10 +69,10 @@
#define CLOCK_CORECLOCK (CONFIG_CLOCK_HSE)

#elif IS_ACTIVE(CONFIG_USE_CLOCK_PLL)
#define CLOCK_CORECLOCK (((CLOCK_PLL_SRC / CONFIG_CLOCK_PLL_M) * CONFIG_CLOCK_PLL_N) / CONFIG_CLOCK_PLL_P)

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#endif /* CONFIG_USE_CLOCK_PLL */

#define CLOCK_PLLQ (((CLOCK_PLL_SRC / CONFIG_CLOCK_PLL_M) * CONFIG_CLOCK_PLL_N) / CONFIG_CLOCK_PLL_Q)

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#define CLOCK_AHB CLOCK_CORECLOCK
#define CLOCK_APB1 (CLOCK_CORECLOCK / CONFIG_CLOCK_APB1_DIV)
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3 changes: 3 additions & 0 deletions cpu/stm32/include/clk/f2f4f7/cfg_clock_default_100.h
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Expand Up @@ -23,6 +23,9 @@
#ifndef CLK_F2F4F7_CFG_CLOCK_DEFAULT_100_H
#define CLK_F2F4F7_CFG_CLOCK_DEFAULT_100_H

#include "kernel_defines.h"
#include "macros/units.h"

#ifdef __cplusplus
extern "C" {
#endif
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3 changes: 3 additions & 0 deletions cpu/stm32/include/clk/f2f4f7/cfg_clock_default_120.h
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#ifndef CLK_F2F4F7_CFG_CLOCK_DEFAULT_120_H
#define CLK_F2F4F7_CFG_CLOCK_DEFAULT_120_H

#include "kernel_defines.h"
#include "macros/units.h"

#ifdef __cplusplus
extern "C" {
#endif
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3 changes: 3 additions & 0 deletions cpu/stm32/include/clk/f2f4f7/cfg_clock_default_180.h
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Expand Up @@ -23,6 +23,9 @@
#ifndef CLK_F2F4F7_CFG_CLOCK_DEFAULT_180_H
#define CLK_F2F4F7_CFG_CLOCK_DEFAULT_180_H

#include "kernel_defines.h"
#include "macros/units.h"

#ifdef __cplusplus
extern "C" {
#endif
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3 changes: 3 additions & 0 deletions cpu/stm32/include/clk/f2f4f7/cfg_clock_default_216.h
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#ifndef CLK_F2F4F7_CFG_CLOCK_DEFAULT_216_H
#define CLK_F2F4F7_CFG_CLOCK_DEFAULT_216_H

#include "kernel_defines.h"
#include "macros/units.h"

#ifdef __cplusplus
extern "C" {
#endif
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3 changes: 3 additions & 0 deletions cpu/stm32/include/clk/f2f4f7/cfg_clock_default_84.h
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#ifndef CLK_F2F4F7_CFG_CLOCK_DEFAULT_84_H
#define CLK_F2F4F7_CFG_CLOCK_DEFAULT_84_H

#include "kernel_defines.h"
#include "macros/units.h"

#ifdef __cplusplus
extern "C" {
#endif
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4 changes: 4 additions & 0 deletions cpu/stm32/include/clk/g0g4/cfg_clock_default.h
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Expand Up @@ -23,6 +23,10 @@
#ifndef CLK_G0G4_CFG_CLOCK_DEFAULT_H
#define CLK_G0G4_CFG_CLOCK_DEFAULT_H

#include "cfg_clock_common_fx_gx_mp1_c0.h"
#include "kernel_defines.h"
#include "macros/units.h"

#ifdef __cplusplus
extern "C" {
#endif
Expand Down Expand Up @@ -103,12 +107,12 @@
#ifndef CONFIG_CLOCK_APB1_DIV
#define CONFIG_CLOCK_APB1_DIV (1)
#endif
#define CLOCK_APB1 (CLOCK_CORECLOCK / CONFIG_CLOCK_APB1_DIV) /* max: 64MHz (G0), 170MHZ (G4) */

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#ifdef CPU_FAM_STM32G4
#ifndef CONFIG_CLOCK_APB2_DIV
#define CONFIG_CLOCK_APB2_DIV (1)
#endif
#define CLOCK_APB2 (CLOCK_AHB / CONFIG_CLOCK_APB2_DIV) /* max: 170MHz (only on G4) */

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#endif
/** @} */

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3 changes: 3 additions & 0 deletions cpu/stm32/include/clk/l0l1/cfg_clock_default.h
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Expand Up @@ -19,6 +19,9 @@
#ifndef CLK_L0L1_CFG_CLOCK_DEFAULT_H
#define CLK_L0L1_CFG_CLOCK_DEFAULT_H

#include "cfg_clock_common_lx_u5_wx.h"
#include "kernel_defines.h"
#include "macros/units.h"
#include "periph_cpu.h"

#ifdef __cplusplus
Expand Down Expand Up @@ -71,7 +74,7 @@
* PLL_MUL: multiplier, allowed values: 3, 4, 6, 8, 12, 16, 24, 32, 48. Default is 4.
* CORECLOCK -> 32MHz MAX!
*/
#define CLOCK_CORECLOCK ((CLOCK_PLL_SRC * CONFIG_CLOCK_PLL_MUL) / CONFIG_CLOCK_PLL_DIV)

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#if CLOCK_CORECLOCK > MHZ(32)
#error "SYSCLK cannot exceed 32MHz"
#endif
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4 changes: 4 additions & 0 deletions cpu/stm32/include/clk/l4l5wx/cfg_clock_default.h
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Expand Up @@ -21,6 +21,10 @@
#ifndef CLK_L4L5WX_CFG_CLOCK_DEFAULT_H
#define CLK_L4L5WX_CFG_CLOCK_DEFAULT_H

#include "cfg_clock_common_lx_u5_wx.h"
#include "kernel_defines.h"
#include "macros/units.h"

#ifdef __cplusplus
extern "C" {
#endif
Expand Down Expand Up @@ -170,11 +174,11 @@
#ifndef CONFIG_CLOCK_APB1_DIV
#define CONFIG_CLOCK_APB1_DIV (4)
#endif
#define CLOCK_APB1 (CLOCK_AHB / CONFIG_CLOCK_APB1_DIV) /* PCLK1, max: 48/64/80/120MHz */

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#ifndef CONFIG_CLOCK_APB2_DIV
#define CONFIG_CLOCK_APB2_DIV (2)
#endif
#define CLOCK_APB2 (CLOCK_AHB / CONFIG_CLOCK_APB2_DIV) /* PCLK1, max: 48/64/80/120MHz */

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/** @} */

#ifdef __cplusplus
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4 changes: 4 additions & 0 deletions cpu/stm32/include/clk/mp1/cfg_clock_default.h
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#ifndef CLK_MP1_CFG_CLOCK_DEFAULT_H
#define CLK_MP1_CFG_CLOCK_DEFAULT_H

#include "cfg_clock_common_fx_gx_mp1_c0.h"
#include "kernel_defines.h"
#include "macros/units.h"

/**
* @name MP1 clock PLL settings (208MHz)
* @{
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4 changes: 4 additions & 0 deletions cpu/stm32/include/clk/u5/cfg_clock_default.h
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#ifndef CLK_U5_CFG_CLOCK_DEFAULT_H
#define CLK_U5_CFG_CLOCK_DEFAULT_H

#include "cfg_clock_common_lx_u5_wx.h"
#include "kernel_defines.h"
#include "macros/units.h"

#ifdef __cplusplus
extern "C" {
#endif
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