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cpu/native: Support native64
Board on ARM
#20739
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Cool! Let me know when you need a review. I can also aid in testing as I have an Apple Silicon ARM PC at hand. |
native64
Board on ARMnative64
Board on ARM
native64
Board on ARMnative64
Board on ARM
@Teufelchen1 PR is ready for review :) |
Thanks for waiting. I noticed a few things, maybe I have an invalid setup for testing or this PR need more work.
Does that sound reasonable to you? Would you expect everything to work with the given setup? Following things did not work as expected:
If needed, I can also arrange a plain linux on ARM64 environment. |
Thank‘s for testing. These issues definitely need to be resolved first, I’m going to try and figure out what’s going on there with these non-functional examples.. On ARM 64 bit, building for 32 bit platforms with gcc seems to be inherently impossible due to lacking gcc multilib support, at least to my knowledge.. Your setup seems fine and similar to mine. What is it exactly you had in mind when you said »we should handle that case more gracefully«? A pretty error message with a reference to RIOT‘s doc perhaps.. carl |
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This branch also works for the Raspberry Pi devices used by for the exercises. Skimming the discussion I'm afraid we won't get this merged by tomorrow so it could go into this summit's tutorials :-) Could you add a branch to |
Contribution Description.
This PR adds support for the
native64
board on arm64/aarch641-m32
and-m64
flags on ARM (?) (hencegcc-multilib
is unavailable on ARM),-mXX
flags are omitted when they would matchgetconf LONG_BIT
Testing procedure (GNU/Linux)
Compile and run on an ARM 64-bit CPU.
Footnotes
Why? E.g., with 64-bit ARM support, you can use the native board on Apple Silicon Macs in a Linux-based virtualized environment (i.e., multipass (or qemu directly), Docker, Virtualization.framework or Hypervisor.framework), without having to resort to emulating a 32-bit ARM or x86 CPU. ↩
For anyone else also wondering how the PC can be set on ARM 64-bit, v8, while preserving all general-purpose registers: You don't. On ARMv8,
PC
cannot be written to anymore, and branch instructions (and friends) either require a static address (which isn't available to us (stored in_native_saved_eip
) or a register containing the destination address. If you look at the glibc implementation ofsetcontext
(which lets you set the instruction pointer) in glibc'ssetcontext.S
, you'll noticex16
is used as the register for thebr
instruction. This PR adopts the same technique. ↩