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cpu/stm32: add ADC support for WB55 #20773
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I have the board somewhere at home. I can give it a try this weekend.
ADC_RES_12BIT = (0x0), /**< ADC resolution: 12 bit */ | ||
ADC_RES_14BIT = (0x1), /**< not applicable */ | ||
ADC_RES_16BIT = (0x2) /**< not applicable */ |
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driver will reject the resolution if the value is 0x03 (dunno why 0x03 though) but it might be a good idea to use this value to reject these resolution and thus prevent misconfiguration.
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Or maybe update the driver to use these values instead to reject the configuration.
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driver will reject the resolution if the value is 0x03 (dunno why 0x03 though) but it might be a good idea to use this value to reject these resolution and thus prevent misconfiguration.
That's not quite accurate, the driver will reject the resolution if the value can be masked by 0x03. This is true for the 0x01 and 0x02 values. In binary it makes more sense: The mask is 0b0011 and the illegal values are 0b0001 and 0b0010.
0b0011 & 0b0001 = 0b0001, 0b0011 & 0b0010 = 0b0010.
Since the resolution bits RES in the ADC_CFGR register are at position 3 and 4, this can be used to find the two illegal values.
IMO this is not a very pretty solution since it relies on magic numbers and it is not obviously documented. But it seems to be the same for all other ADC implementations as well. For now I wouldn't change it though.
(This part of the code is just copied from the cpu/stm32/include/periph/l4/periph_cpu.h file. It is the same for the L4 and WB55.)
STM32WB55 Reference Manual: https://www.st.com/resource/en/reference_manual/rm0434-multiprotocol-wireless-32bit-mcu-armbased-cortexm4-with-fpu-bluetooth-lowenergy-and-802154-radio-solution-stmicroelectronics.pdf page 489
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Then you could borrow the behavior from here which is more easy to understand.
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Then you could borrow the behavior from here which is more easy to understand.
I generally agree with you, but I didn't change anything in the cpu/stm32/periph/adc_l4.c file in this PR. I just renamed it and changed the cpu/stm32/include/wb/periph_cpu.h file to be compatible with the data structures that adc_l4.c expects.
A better approach would be to create a new issue/PR to fix this issue for the other boards in one go, so we can keep things separate:
https://github.com/RIOT-OS/RIOT/blob/master/cpu/stm32/periph/adc_f0_g0_c0.c#L103-L106
https://github.com/RIOT-OS/RIOT/blob/master/cpu/stm32/periph/adc_f2.c#L112-L114
https://github.com/RIOT-OS/RIOT/blob/master/cpu/stm32/periph/adc_f3.c#L196-L199
https://github.com/RIOT-OS/RIOT/blob/master/cpu/stm32/periph/adc_f4_f7.c#L131-L134
https://github.com/RIOT-OS/RIOT/blob/master/cpu/stm32/periph/adc_wl.c#L121-L124
Better examples that don't rely on magic numbers:
https://github.com/RIOT-OS/RIOT/blob/master/cpu/stm32/periph/adc_f1.c#L146-L149
https://github.com/RIOT-OS/RIOT/blob/master/cpu/stm32/periph/adc_l0.c#L120-L126
https://github.com/RIOT-OS/RIOT/blob/master/cpu/stm32/periph/adc_l1.c#L149-L155
Thank you. Remember that this PR depends on #20756, so you have to apply the changes of that PR to the adc_l4_wb.c file. |
Feel free to rebase (ans squash the new extra commit) whenever you want. |
Done. This was a learning experience. Apparently it is not a good idea to use the convenient "sync" button in Github, because it leaves this merge commit and now all the commits that happened since are in the commit history. And merge commits can not be squashed 🙃 Now the PR has the #20756 PR incorporated and you should be able to test it now as it is :) |
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Tested on p-nucleo-wb55. I was only able to test GND and 3V3 levels but this is looking good.
thanks !
At first glance, I would say 'wb' must be added there |
please squash. |
Round 2 ! |
Thank you @dylad for your comprehensive help :) |
Thanks for your contribution :) |
Contribution description
As described in the issue #17260, the ADC in the STM32WB55 has the same basic peripheral as the STM32L4 series, therefore the ADC implementation can be shared between these devices.
Edit: During the creation of this PR I found an error in the P-NUCLEO-WB55 user manual: https://www.st.com/resource/en/user_manual/um2435-bluetooth-low-energy-and-802154-nucleo-pack-based-on-stm32wb-series-microcontrollers-stmicroelectronics.pdf
In Table 10 on page 39, ADC1_IN5 and ADC1_IN6 are switched.
The datasheet is correct: https://www.st.com/resource/en/datasheet/stm32wb55cc.pdf Table 17 page 69.
Testing procedure
The tests/periph/adc test should run successfully on a P-NUCLEO-WB55 board with this PR applied (and #20756).
To compile the test I ran the following command:
And this is the console output. The correct ADC lines can be verified by pulling the A0-A5 pins to GND and +3V3 respectively. To test the VBAT channel, SB30 has to be closed (or you can touch SB30 with a jumper cable which is connected to +3V3 on the other side).
Issues/PRs references
Fixes #17260.
Depends on #20756, because with the mainline RIOT code, the ADC initialization does not work.
This will require a rebase when #20756 is merged because this PR changes the name of adc_l4.c to adc_l4_wb.c