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Thumb: Implement MultipleLoadStore
#189
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Codecov ReportPatch coverage:
❗ Your organization is not using the GitHub App Integration. As a result you may experience degraded service beginning May 15th. Please install the Github App Integration for your organization. Read more. Additional details and impacted files@@ Coverage Diff @@
## main #189 +/- ##
==========================================
+ Coverage 57.13% 57.54% +0.40%
==========================================
Files 37 37
Lines 2753 2777 +24
==========================================
+ Hits 1573 1598 +25
+ Misses 1180 1179 -1
☔ View full report in Codecov by Sentry. |
emu/src/cpu/arm7tdmi.rs
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let base_address = self.registers.register_at(base_register as usize); | ||
for r in 0..=7 { | ||
if register_list.get_bit(r) { | ||
let address = base_address + (r as u32 * 4); |
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I'm not sure this is correct, imagine a register list like this: 0b00000010
and R0 = 0x100
. We should then read at 0x100
and write in R1
. But with this logic we read in 0x104
, right?
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You are right! Fixed the behavior, only increment if bit is true :)
let mut registers = String::new(); | ||
for i in 0..=7 { | ||
if register_list.get_bit(i) { | ||
registers.push_str(&format!("R{}, ", i)); |
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Like this we would have {R0, R1, }
, right? (I mean at the end we would have an additional comma).
Also, to be consistent with the datasheet we should use -
to separate registers :P
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I know... Right now I took a shortcut :D we can leave as good first issue :) (another instruction has this problem) :D
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Signed-off-by: Federico Guerinoni <guerinoni.federico@gmail.com>
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This implements only the part clementine needs to pass the step. We should improve testing and splitting better files like module
arm
and modulethumb