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[WaveTransform] Missing clang-format on commit by PR #473. #487

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Merged
merged 1 commit into from
Nov 4, 2025
Merged

[WaveTransform] Missing clang-format on commit by PR #473. #487

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3 changes: 2 additions & 1 deletion llvm/lib/Target/AMDGPU/AMDGPULaneMaskUtils.h
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Original file line number Diff line number Diff line change
Expand Up @@ -70,7 +70,8 @@ class LaneMaskConstants {
XorOpc(IsWave32 ? AMDGPU::S_XOR_B32 : AMDGPU::S_XOR_B64),
XorTermOpc(IsWave32 ? AMDGPU::S_XOR_B32_term : AMDGPU::S_XOR_B64_term),
WQMOpc(IsWave32 ? AMDGPU::S_WQM_B32 : AMDGPU::S_WQM_B64),
LaneMaskRC(IsWave32 ? &AMDGPU::SReg_32RegClass : &AMDGPU::SReg_64RegClass) {}
LaneMaskRC(IsWave32 ? &AMDGPU::SReg_32RegClass
: &AMDGPU::SReg_64RegClass) {}

static inline const LaneMaskConstants &get(const GCNSubtarget &ST);
};
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4 changes: 2 additions & 2 deletions llvm/lib/Target/AMDGPU/AMDGPUWaveTransform.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1841,8 +1841,8 @@ void ControlFlowRewriter::rewrite() {
Register CondReg = Info.OrigCondition;
if (!LMA.isSubsetOfExec(CondReg, *Node->Block)) {
CondReg = LMU.createLaneMaskReg();
BuildMI(*Node->Block, Node->Block->end(), {},
TII.get(LMC.AndOpc), CondReg)
BuildMI(*Node->Block, Node->Block->end(), {}, TII.get(LMC.AndOpc),
CondReg)
.addReg(LMC.ExecReg)
.addReg(Info.OrigCondition);
}
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13 changes: 6 additions & 7 deletions llvm/lib/Target/AMDGPU/GCNLaneMaskUtils.cpp
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Expand Up @@ -151,10 +151,9 @@ void GCNLaneMaskUtils::buildMergeLaneMasks(MachineBasicBlock &MBB,
CurMaskedReg = CurReg;
} else {
CurMaskedReg = createLaneMaskReg();
CurMaskedBuilt =
BuildMI(MBB, I, DL, TII->get(LMC.AndOpc), CurMaskedReg)
.addReg(CurReg)
.addReg(LMC.ExecReg);
CurMaskedBuilt = BuildMI(MBB, I, DL, TII->get(LMC.AndOpc), CurMaskedReg)
.addReg(CurReg)
.addReg(LMC.ExecReg);
}
}

Expand Down Expand Up @@ -268,7 +267,7 @@ bool GCNLaneMaskAnalysis::isSubsetOfExec(Register Reg,
void GCNLaneMaskUpdater::init(Register Reg) {
Processed = false;
Blocks.clear();
//SSAUpdater.Initialize(LMU.getLaneMaskConsts().LaneMaskRC);
// SSAUpdater.Initialize(LMU.getLaneMaskConsts().LaneMaskRC);
SSAUpdater.Initialize(Reg);
}

Expand Down Expand Up @@ -418,8 +417,8 @@ void GCNLaneMaskUpdater::process() {
// Prepare an all-zero value for the default and reset in accumulating mode.
if (Accumulating && !ZeroReg) {
ZeroReg = LMU.createLaneMaskReg();
BuildMI(Entry, Entry.getFirstTerminator(), {}, TII->get(LMU.getLaneMaskConsts().MovOpc),
ZeroReg)
BuildMI(Entry, Entry.getFirstTerminator(), {},
TII->get(LMU.getLaneMaskConsts().MovOpc), ZeroReg)
.addImm(0);
}

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9 changes: 4 additions & 5 deletions llvm/lib/Target/AMDGPU/GCNLaneMaskUtils.h
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Original file line number Diff line number Diff line change
Expand Up @@ -35,13 +35,12 @@ class GCNLaneMaskUtils {

public:
GCNLaneMaskUtils() = delete;
explicit GCNLaneMaskUtils(MachineFunction &MF) : MF(MF),
LMC(AMDGPU::LaneMaskConstants::get(MF.getSubtarget<GCNSubtarget>())) {}
explicit GCNLaneMaskUtils(MachineFunction &MF)
: MF(MF),
LMC(AMDGPU::LaneMaskConstants::get(MF.getSubtarget<GCNSubtarget>())) {}

MachineFunction *function() const { return &MF; }
const AMDGPU::LaneMaskConstants &getLaneMaskConsts() const {
return LMC;
}
const AMDGPU::LaneMaskConstants &getLaneMaskConsts() const { return LMC; }

bool maybeLaneMask(Register Reg) const;
bool isConstantLaneMask(Register Reg, bool &Val) const;
Expand Down