Layernorm optimizations #8
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Bulk conversions (packed halfs into half2, using vectors of half2); block and warp reduce with AMD wavesize 64 (vs 32); using smaller block sizes for improved block occupancy on CUs
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This PR introduces performance optimizations for fused_add_rms_norm, used in various layernorms. Its primary features are the use of packed operations for FP16 and also the use of batched ("vectorized") loads and stores, reflecting the fact that this kernel is memory latency-bound. It also decreases the maximum block size to 256 to enable better simultaneous scheduling of blocks onto SIMDs for better memory latency hiding.
Other miscellaneous additions include a more general implementation of ROCm-specific wavesizes of 64 instead of CUDA's 32 for the Alford warp shuffle.