assign doesn't handle implicitely created wires in the LHS

[smunaut]

I'm not 100% sure from the LRM but when cross-checking the vehavior of a couple of verilog parsers, the LHS of an assign statement doesn't have to be pre-declared using a wire statement. That doesn't work for the bracket notation.

So :

wire x;
assign test = x;

is valid, but

wire x;
assign test[1] = x;

is not for instance.

Currently netgen doesn't accept that. See included reproducer that ends up with 'pin matching failed'.

netgen_bug.tar.gz

I'll open a PR with a proposed fix that basically creates the node as needed.
I'm not 100% sure it's the correct fix, but it seems to fix this particular reproducer, but please double check it's actually the right thing to do.