Pin verification #215 (fix)

SiEPIC · Jul 18, 2024 · 4cf1be8 · 4cf1be8
1 parent 0f4d0d2
commit 4cf1be8
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Showing 2 changed files with 26 additions and 27 deletions.
diff --git a/klayout_dot_config/python/SiEPIC/verification.py b/klayout_dot_config/python/SiEPIC/verification.py
@@ -412,32 +412,31 @@ def layout_check(cell=None, verbose=False, GUI=False, timing=False, file_rdb = N
         # check all the component's pins to check if they are assigned a net:
         r1 = pya.Region(c.polygon) # Component's DevRec region
         for pin in c.pins:
-            if pin.type == _globals.PIN_TYPES.OPTICAL and pin.net.idx == None:
-                # disconnected optical pin
-                if verbose:
-                    print(" - Found disconnected pin, type %s, at (%s)" % (pin.type, pin.center))
-                    pin.display()
-                rdb_item = rdb.create_item(rdb_cell.rdb_id(), rdb_cat_id_discpin.rdb_id())
-                rdb_item.add_value(pya.RdbItemValue(pin.path.to_dtype(dbu)))
-
-            # Check for pin errors, facing the wrong way in the Component
-            # ***** 
-            pts = pin.path.get_points()[0]
-            px, py = pts.x, pts.y
-            test_box = pya.Box(px - 1, py - 1, px + 1, py + 1)
-            r2 = pya.Region(test_box)
-            polygon_and = [p for p in r1 & r2]
-            if not polygon_and: 
-                # Pin's first point is not inside the DevRec
-                test_box = pya.Box(px - 5, py - 5, px + 5, py + 5)
-                rdb_item = rdb.create_item(rdb_cell.rdb_id(), rdb_cat_id_comp_pinerrors.rdb_id())
-                rdb_item.add_value(pya.RdbItemValue(pya.Polygon(test_box).to_dtype(dbu)))
-                rdb_item.add_value(pya.RdbItemValue(
-                    "The components with the pin problem is: " + c.component))
-                if verbose:
-                    print (str(test_box))
-
-
+            if pin.type == _globals.PIN_TYPES.OPTICAL:
+                if pin.net.idx == None:
+                    # disconnected optical pin
+                    if verbose:
+                        print(" - Found disconnected pin, type %s, at (%s)" % (pin.type, pin.center))
+                        pin.display()
+                    rdb_item = rdb.create_item(rdb_cell.rdb_id(), rdb_cat_id_discpin.rdb_id())
+                    rdb_item.add_value(pya.RdbItemValue(pin.path.to_dtype(dbu)))
+
+                # Check for pin errors, facing the wrong way in the Component
+                # ***** 
+                pts = pin.path.get_points()[0]
+                px, py = pts.x, pts.y
+                test_box = pya.Box(px - 1, py - 1, px + 1, py + 1)
+                r2 = pya.Region(test_box)
+                polygon_and = [p for p in r1 & r2]
+                if not polygon_and: 
+                    # Pin's first point is not inside the DevRec
+                    test_box = pya.Box(px - 5, py - 5, px + 5, py + 5)
+                    rdb_item = rdb.create_item(rdb_cell.rdb_id(), rdb_cat_id_comp_pinerrors.rdb_id())
+                    rdb_item.add_value(pya.RdbItemValue(pya.Polygon(test_box).to_dtype(dbu)))
+                    rdb_item.add_value(pya.RdbItemValue(
+                        "The components with the pin problem is: " + c.component))
+                    if verbose:
+                        print (str(test_box))
 
         # Verification: overlapping components (DevRec)
             # automatically takes care of waveguides crossing other waveguides & components

diff --git a/klayout_dot_config/tech/GSiP/pymacros/tests/test_example_circuit.py b/klayout_dot_config/tech/GSiP/pymacros/tests/test_example_circuit.py
@@ -108,7 +108,7 @@ def example_circuit():
     print (text)
 
     # Verify
-    num_errors = layout_check(cell=cell, verbose=True, GUI=True)
+    num_errors = layout_check(cell=cell, verbose=False, GUI=True)
     print('Number of errors: %s' % num_errors)
 
     # Netlist