- The Canadian Silicon Photonics Foundry, SiEPICfab, presents the open electron beam lithography (EBL) fabrication process, where former and current students of SiEPIC workshops and courses can submit their design for manufacturing and testing.
- More details about openEBL.
- SOI wafer, 220 nm silicon
- Baseline process:
- Single full etch, using a negative resist (HSQ)
- Oxide cladding
- TiW metal heater, and Au metal bond pads
- Details: Slides
- Process Design Kit: SiEPIC-EBeam-PDK
| Name | Layer/datatype | Description |
|---|---|---|
| Si | 1/99 | Layer to draw silicon geometries |
| M1_heater | 11/0 | Layer to draw metal heater, TiW |
| M2_router | 12/0 | Layer to draw metal routing, Au |
| Floorplan | 99/0 | Marks the layout design area |
| Text | 10/0 | Text labels for automated measurements |
| DevRec | 68/0 | Device recognition layer for component connectivity, netlist extraction, and verification |
| PinRec | 1/10 | Port/pins recognition layer for component connectivity, netlist extraction, and verification |
| Waveguide | 1/99 | Virtual layer, guiding shape for waveguides |
| SEM | 200/0 | Requests for SEM images. Rectangles in a 4:3 aspect |
The submission involves several steps. First, you need to create your design(s) using the process design kit (PDK) for this specific fabrication run. Then you need to create a Fork of this repository, commit your design(s), ensure that it passes the checks, and create a pull request. Once your pull request is approved, your design(s) will be merged into the layout for fabrication. You should verify that your design is correctly merged. Once the designs are fabricated, they will be tested, and the measurement results will be posted in this repository.
- Design tools and process design kit (SiEPIC-EBeam-PDK, KLayout implementation)installation instructions.
- Create an account on GitHub
- Fork a copy of this GitHub repository into your own account: Create a new fork
- [Optional] Install GitHub Desktop (or git) on your computer, and Clone a local copy: Open with GitHub Desktop
- Create your design, and ensure that the filename contains your edX.org username, and be formatted according to the course/workshop as follows:
- EBeam_username.oas: for the edX Phot1x silicon photonics design course
- ELEC413_username.oas: for the UBC ELEC 413 course
- SiEPIC_Passives_username.oas: for the CMC SiEPIC Passives silicon photonics workshop
- For example: EBeam_LukasChrostowski_rings.oas
- Create your YAML test routines file, following the same filename requirements as above, but ending with extension .yaml.
- Upload your design(s) into the "submissions" folder, as a binary file, namely a .gds (GDSII format) or .oas (OASIS format) file, and the YAML test routine file.
- This can be done via the GitHub web page, by navigating to the submissions folder, then clicking on Add file, and Upload files.
- Click Commit changes, and wait for the verification to complete
- If there are errors, please review and correct the errors
- Alternatively upload your Python file, which will be compiled by a GitHub Action.
- For KLayout designs, use the "submissions/KLayout Python" folder, namely a .py (Python format) file. e.g., EBeam_LukasChrostowski_MZI.py. The Python file should save a gds or oas file into the parent "submissions" folder. The Python script needs to be executable in non-GUI mode, namely using "import klayout SiEPIC SiEPIC-EBeam-PDK"
- Check below for the merged design, and ensure that your design is correctly included
- Create a Pull Request -- this will notify the team of your contribution, which we can aggregate into the main design file
- Return to the main repository, and check for the merged design
- We perform IP replacement on several cells (grating couplers). We call these cells Black Box (BB), and you can identify them by _BB in the cell name, or the presence of the Blackbox layer 998/0 in the cell.
- You must not change the name of the cell, the contents, nor cell origins. Otherwise, the replacement will not work correctly.
- Running the files in the "submissions/KLayout Python" folder, to generate the designs
- Performing Manufacturing DRC verification on the designs in the "submissions" folder, and outputing the errors as an Artifact
- Performing Functional verification on the designs in the "submissions" folder, and outputing the errors as an Artifact
- Merging the designs from the "submissions" folder, and outputing merged layout as an Artifact