plat/nxp: set L2 cache data and tag RAM latency

Signed-off-by: Andrew Yong <me@ndoo.sg>
SolidRun · Oct 9, 2024 · 34dd1a0 · 34dd1a0
1 parent a28799c
commit 34dd1a0
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Showing 2 changed files with 15 additions and 1 deletion.
diff --git a/plat/nxp/common/aarch64/ls_helpers.S b/plat/nxp/common/aarch64/ls_helpers.S
@@ -6,8 +6,8 @@
  */
 
 #include <asm_macros.S>
+#include <cortex_a72.h>
 #include <drivers/console.h>
-#include <lib/cpus/aarch64/cortex_a72.h>
 
 #include <platform_def.h>
 
@@ -23,6 +23,7 @@
 	.globl _disable_ldstr_pfetch_A53
 	.globl _disable_ldstr_pfetch_A72
 	.global	_set_smmu_pagesz_64
+	.global _set_l2_latency
 
 	/* int plat_crash_console_init(void)
 	 * Function to initialize the crash console
@@ -192,3 +193,15 @@ func _set_smmu_pagesz_64
 
 	ret
 endfunc _set_smmu_pagesz_64
+
+/*
+ * Function sets L2 cache data RAM latency to 4 cycles
+ */
+func _set_l2_latency
+
+	mov x0, #((5 << CORTEX_A72_L2CTLR_DATA_RAM_LATENCY_SHIFT) |	\
+			 (0x1 << 5))
+	isb
+
+	ret
+endfunc _set_l2_latency
diff --git a/plat/nxp/soc-lx2160a/aarch64/lx2160a_helpers.S b/plat/nxp/soc-lx2160a/aarch64/lx2160a_helpers.S
@@ -37,6 +37,7 @@ func plat_reset_handler
 	bl  apply_platform_errata
 
 #if defined(IMAGE_BL31)
+	bl _set_l2_latency
 	ldr x0, =POLICY_SMMU_PAGESZ_64K
 	cbz x0, 1f
 	/* Set the SMMU page size in the sACR register */