plat/nxp: set L2 cache ECC and and parity on A72 cores

Signed-off-by: Andrew Yong <me@ndoo.sg>

plat/nxp/common/aarch64/ls_helpers.S

@@ -195,19 +195,32 @@ func _set_smmu_pagesz_64
 endfunc _set_smmu_pagesz_64
 
 func _delay_exclusive_snoop_A72
-        mrs     x0, CORTEX_A72_CPUACTLR_EL1
-        tst     x0, #CORTEX_A72_CPUACTLR_EL1_DELAY_EXCLUSIVE_SNOOP
-        b.eq    1f
-        b       2f
+
+	mrs x0, CORTEX_A72_L2CTLR_EL1
+	/* Enable L2 ECC and parity with inline data */
+	orr		x0, x0, #CORTEX_A72_L2CTLR_EL1_ECC_AND_PARITY_ENABLE
+	orr		x0, x0, #CORTEX_A72_L2CTLR_EL1_DATA_INLINE_ECC_ENABLE
+	msr		CORTEX_A72_L2CTLR_EL1, x0
+
+	mrs 	x0, CORTEX_A72_L2ACTLR_EL1
+	/* Enable L2 UniqueClean evictions with data */
+	orr		x0, x0, #CORTEX_A72_L2ACTLR_ENABLE_UNIQUE_CLEAN
+	msr		CORTEX_A72_L2ACTLR_EL1, x0
+
+	mrs     x0, CORTEX_A72_CPUACTLR_EL1
+	/* Set Snoop-delayed exclusive handling */
+	tst     x0, #CORTEX_A72_CPUACTLR_EL1_DELAY_EXCLUSIVE_SNOOP
+	b.eq    1f
+	b       2f
 
 .align 6
 1:
-        dsb     sy
-        isb
-        orr     x0, x0, #CORTEX_A72_CPUACTLR_EL1_DELAY_EXCLUSIVE_SNOOP
-        msr     CORTEX_A72_CPUACTLR_EL1, x0
-        isb
+	dsb     sy
+	isb
+	orr     x0, x0, #CORTEX_A72_CPUACTLR_EL1_DELAY_EXCLUSIVE_SNOOP
+	msr     CORTEX_A72_CPUACTLR_EL1, x0
+	isb
 
 2:
-        ret
+	ret
 endfunc _delay_exclusive_snoop_A72