rcw: clearfog-cx: support serdes 1 protocol 4 (8x 1Gbps)

SolidRun · Nov 7, 2024 · 69642e2 · 69642e2
1 parent c8099c8
commit 69642e2
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Showing 4 changed files with 3,094 additions and 8 deletions.
diff --git a/patches/rcw/0017-lx2160acex7-add-configuration-for-serdes-1-protocol-.patch b/patches/rcw/0017-lx2160acex7-add-configuration-for-serdes-1-protocol-.patch
@@ -1,4 +1,4 @@
-From d232fbff1960d7f3606bb172157dd4815296be3e Mon Sep 17 00:00:00 2001
+From cbb5b8743e3790dd9172a6b9146e60dfaec221ac Mon Sep 17 00:00:00 2001
 From: Josua Mayer <josua@solid-run.com>
 Date: Wed, 6 Nov 2024 11:18:12 +0100
 Subject: [PATCH] lx2160acex7: add configuration for serdes 1 protocol 4
@@ -9,16 +9,16 @@ Therefore no board configuration has been added beyond the include.
 
 Signed-off-by: Josua Mayer <josua@solid-run.com>
 ---
- lx2160acex7/include/SD1_4.rcwi | 26 ++++++++++++++++++++++++++
- 1 file changed, 26 insertions(+)
+ lx2160acex7/include/SD1_4.rcwi | 25 +++++++++++++++++++++++++
+ 1 file changed, 25 insertions(+)
  create mode 100644 lx2160acex7/include/SD1_4.rcwi
 
 diff --git a/lx2160acex7/include/SD1_4.rcwi b/lx2160acex7/include/SD1_4.rcwi
 new file mode 100644
-index 0000000..aea0c13
+index 0000000..3c6023a
 --- /dev/null
 +++ b/lx2160acex7/include/SD1_4.rcwi
-@@ -0,0 +1,26 @@
+@@ -0,0 +1,25 @@
 +/*
 + * Serdes 1 Reference Clocks:
 + * - PLLF = 161.1328125MHz
@@ -37,7 +37,6 @@ index 0000000..aea0c13
 +
 +/* Enable PLLS */
 +SRDS_PLL_PD_PLL2=0
-+SRDS_REFCLKS_DIS_S1=0
 +
 +/*
 + * Select PLLF frequency 100MHz (don't care): Bit 0 = 0