atf/rcw: add sdram configuration for internal cex6 evb revision 1.2

patches/atf/0015-lx2160acex6-add-ddr-configuration-for-pcb-v1.2-with-.patch

@@ -0,0 +1,127 @@
+From 319f6d2f0cbbb54ac56926683c5e0dfefe984e64 Mon Sep 17 00:00:00 2001
+From: Josua Mayer <josua@solid-run.com>
+Date: Sun, 24 Nov 2024 12:38:17 +0100
+Subject: [PATCH] lx2160acex6: add ddr configuration for pcb v1.2 with ecc
+
+Tune DDR Configuration for v1.1 PCB with MIcron memory, and v1.2 PCB
+resolving ECC issues.
+
+Signed-off-by: Josua Mayer <josua@solid-run.com>
+---
+ plat/nxp/soc-lx2160a/lx2160acex6/ddr_init.c  | 42 +++++++++++++-------
+ plat/nxp/soc-lx2160a/lx2160acex6/platform.mk |  3 +-
+ 2 files changed, 29 insertions(+), 16 deletions(-)
+
+diff --git a/plat/nxp/soc-lx2160a/lx2160acex6/ddr_init.c b/plat/nxp/soc-lx2160a/lx2160acex6/ddr_init.c
+index 0b978e298..61acfd7ac 100644
+--- a/plat/nxp/soc-lx2160a/lx2160acex6/ddr_init.c
++++ b/plat/nxp/soc-lx2160a/lx2160acex6/ddr_init.c
+@@ -31,21 +31,29 @@
+ #error Not implemented.
+ #endif /* CONFIG_DDR_NODIMM == 1 */
+
+-#if CONFIG_DDR_NODIMM == 2
++#if CONFIG_DDR_NODIMM == 2 || CONFIG_DDR_NODIMM == 3
+ /*
+- * PCB Revision 1.1: 2 x 5 x K4A8G165WB-BCRC
+- *
+- * ECC disabled because of training failures.
++ * PCB Revision 1.1/1.2: 2 x 5 x MT40A1G16TB-062E IT:F
+  */
+ #define CONFIG_DDR_NODIMM_CH2
++
++#if CONFIG_DDR_NODIMM == 3
++/* PCB Revision 1.2 supports ECC */
++#define CONFIG_DDR_NODIMM_ECC
++#endif /* CONFIG_DDR_NODIMM == 3 */
++
+ static const struct dimm_params static_dimm = {
+-	.mpart = "Fixed DDR Config 2",
++	.mpart = "Fixed DDR Config " __XSTRING(CONFIG_DDR_NODIMM),
+ 	.n_ranks = 1,
+ 	.die_density = 0x6, // encoded per spd byte 4, 0b110 = 16Gbit
+-	.rank_density = 0x200000000, // 16GB
+-	.capacity = 0x200000000, // 16GB
++	.rank_density = 0x200000000, // 16Gbit
++	.capacity = 0x200000000, // 16Gbit
+ 	.primary_sdram_width = 64,
++#ifdef CONFIG_DDR_NODIMM_ECC
++	.ec_sdram_width = 8, // 8 bit ecc extension
++#else
+ 	.ec_sdram_width = 0, // no ecc extension
++#endif
+ 	.rdimm = 0,
+ 	.package_3ds = 0,
+ 	.device_width = 16, // 16 bit per sdram
+@@ -53,26 +61,30 @@ static const struct dimm_params static_dimm = {
+
+ 	.n_row_addr = 17,
+ 	.n_col_addr = 10,
++#ifdef CONFIG_DDR_NODIMM_ECC
++	.edc_config = 2, // enable ecc
++#else
+ 	.edc_config = 0, // disable ecc
++#endif
+ 	.bank_addr_bits = 0, // 4 banks
+ 	.bank_group_bits = 1, // 2 bank groups
+ 	.burst_lengths_bitmask = 0xc, // enable 4 & 8-bit burst (DDR4 spec)
+
+ 	.mirrored_dimm = 0,
+
+-	// timings based on K4A8G085WC-BCTD (DDR4-2666), missing values for 3200
++	// timings based on MT40A4G4 / MT40A2G8 / MT40A1G16 datasheet (DDR4-3200 22-22-22)
+ 	.mtb_ps = 125, // MTB per SPD spec
+ 	.ftb_10th_ps = 10, // default value, unused by nxp ddr driver
+ 	.taa_ps = 13750, // min. 13.75ns
+-	.tfaw_ps = 30000, // min: max(30ns or 28CK) (this 16Gbit sdram has 2KB pages)
++	.tfaw_ps = 30000, // min: max(30ns or 28CK) (this 8Gbit sdram has 2KB pages)
+
+-	.tckmin_x_ps = 625, // 3200 (CK=1600)
++	.tckmin_x_ps = 625, // 2400 (CK=1600)
+ 	.tckmax_ps = 1250, // 1600 (CK=800)
+
+-	.caslat_x = 0b00000001010101010101010000000000, // CL = [10,12,14,16,18,20,22,24] (1 << CL)
++	.caslat_x = 0b00000001011111111111110000000000, // CL = [10-22,24] (1 << CL)
+
+-	.trcd_ps = 13750, // 13.75ns - CL22-22-22
+-	.trp_ps = 13750, // 13.75ns - CL22-22-22
++	.trcd_ps = 13750, // 13.75ns
++	.trp_ps = 13750, // 13.75ns
+ 	.tras_ps = 32000, // 32ns
+
+ 	.trfc1_ps = 350000, // 350ns,
+@@ -100,7 +112,7 @@ static const struct dimm_params static_dimm = {
+ 		0x00,
+ 		0x20,
+ 		0x00,
+-		0x00,
++		0x02,
+ 		0x00,
+ 		0x20,
+ 		0x00,
+@@ -112,7 +124,7 @@ static const struct dimm_params static_dimm = {
+ 	},
+ 	.dq_mapping_ors = 1,
+ };
+-#endif /* CONFIG_DDR_NODIMM == 2 */
++#endif /* CONFIG_DDR_NODIMM == 2 || CONFIG_DDR_NODIMM == 3 */
+
+ int ddr_get_ddr_params(struct dimm_params *pdimm,
+ 			    struct ddr_conf *conf)
+diff --git a/plat/nxp/soc-lx2160a/lx2160acex6/platform.mk b/plat/nxp/soc-lx2160a/lx2160acex6/platform.mk
+index 950207878..d01a41ea6 100644
+--- a/plat/nxp/soc-lx2160a/lx2160acex6/platform.mk
++++ b/plat/nxp/soc-lx2160a/lx2160acex6/platform.mk
+@@ -22,7 +22,8 @@ APPLY_MAX_CDD	:=	yes
+
+ # Mock SPD:
+ # - 0: disable mock spd
+-# - 2: 2 x 5 x K4A8G165WB-BCRC PCB v1.1
++# - 2: 2 x 5 x MT40A1G16TB-062E IT:F PCB v1.1
++# - 3: 2 x 5 x MT40A1G16TB-062E IT:F PCB v1.2 (with ECC)
+ CONFIG_DDR_NODIMM	:=	0
+
+ # S5 GPIO
+-- 
+2.43.0
+