Part of ASM code for AVR32DD20 #402
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Can someone help where i'am wrong ? I'am bad in AVR ASM and this is rewritten part of not my code that was working on atmega328. I need it.
ORIGINAL CODE FOR ATMEGA328
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the _SFR_TO_IO_ADDR() macro is meaningless on modern AVRs, the address of SFRs in the I/O space is identical to the address in data space. The registers you need to use are the VPORT registers - VPORTx.OUT and VPORTx.DIR instead of PORTx and DDRx (PORTx is now the name of the full PORT structure in the extended I/O space (specifically, they start at 0x0400 and each one is 32 bytes long: DIR DIRSET DIRCLR DIRTGL, OUT OUTSET, OUTCLR, OUTTGL, IN, INTFLAGS, PORTCTRL (for slew rate limiting), and then the 4 PINCONFIG related registers, then 1 reserved address before the PINnCTRL registers start halfway through the port, and while I did fact check that - I wrote that from memory successfully :-P). Note also that on modern AVRs cbi and sbi are now single-cycle instructions instead of two-cycle ones! ST and STD are also single clock - though ld is still 2, and LDS gained 1 clock cycle You of course can't do cbi/sbi/sbic/sbis on the port registers, only the low IO space (0x0000 to 0x001F), so the PORTx register doesn't do you so much good; hence why the VPORT registers exist - they each mirror a register in the you need the VPORTs. Each port gets 4 VPORT registers in the low I/O space, VPORTx.DIR, VPORTx.OUT, VPORTx.IN and VPORTx.INTFLAGS, in that order, and as you'd expect VPORTA is first at 0x00, VPORTB at 0x04 and so on. After VPORTG.INTFLAGSat 0x1B the last low I/O registers, 0x1C-0x1F are the 4 GPR registers which do absolutely nothing other than allow you to use IN, OUT, SBI, CBI, SBIC, and SBIS on them. And that's it for the low I/O space, and the high I/O space is damned near empty - it's got only 4 or 5 registers in it (CCP, the stack pointer, and the SREG; a part with 256k (note that DxCore provides a #define that points GPIORn to GPR_GPRn, and I think also GPIOn, because between Atmel and Microchip, they've had parts released with three different names for those registers. While GPRn is the most logical name (particularly to people who don't know AVR asm, and hence don't know that they were called the GPIOR's because they're General Purpose registers in the I/O space, that is, the space where the IN and OUT instructions can be used), GPIOR is much more widely known. DxCore also stores the reset cause flags into GPR.GPR0 upon startup as a way to be able to clear them (to make it harder to get the chip into a bad state that would require manual reset to escape) while leaving them available to user code. We describe that in excruciating detail in the reset reference). |
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Now it works , thank you , you are the best! |
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the _SFR_TO_IO_ADDR() macro is meaningless on modern AVRs, the address of SFRs in the I/O space is identical to the address in data space.
The registers you need to use are the VPORT registers - VPORTx.OUT and VPORTx.DIR instead of PORTx and DDRx (PORTx is now the name of the full PORT structure in the extended I/O space (specifically, they start at 0x0400 and each one is 32 bytes long: DIR DIRSET DIRCLR DIRTGL, OUT OUTSET, OUTCLR, OUTTGL, IN, INTFLAGS, PORTCTRL (for slew rate limiting), and then the 4 PINCONFIG related registers, then 1 reserved address before the PINnCTRL registers start halfway through the port, and while I did fact check that - I wrote that from memory successfully :-P).