Got coherent mem view to pass 20 first seconds of linux boot (sim)

SpinalHDL · Aug 3, 2023 · a7a2804 · a7a2804
1 parent 3967223
commit a7a2804
Show file tree

Hide file tree

Showing 5 changed files with 39 additions and 34 deletions.
diff --git a/ext/riscv-isa-sim b/ext/riscv-isa-sim
diff --git a/ext/rvls b/ext/rvls
diff --git a/src/main/scala/naxriscv/lsu/DataCache.scala b/src/main/scala/naxriscv/lsu/DataCache.scala
@@ -96,6 +96,7 @@ case class DataStoreRsp(addressWidth : Int, refillCount : Int) extends Bundle {
  val flush = Bool()
  val prefetch = Bool()
  val address = UInt(addressWidth bits)
+ val io = Bool()
 }
 
 
@@ -1792,6 +1793,7 @@ class DataCache(val p : DataCacheParameters) extends Component {
  io.store.rsp.flush := FLUSH
  io.store.rsp.prefetch := PREFETCH
  io.store.rsp.address := ADDRESS_POST_TRANSLATION
+ io.store.rsp.io := IO
  }
  pipeline.build()
  }

diff --git a/src/main/scala/naxriscv/lsu2/Lsu2Plugin.scala b/src/main/scala/naxriscv/lsu2/Lsu2Plugin.scala
@@ -1141,7 +1141,7 @@ class Lsu2Plugin(var lqSize: Int,
 
  val whitebox = new Area{
  def patch[T <: Data](that : T) : T = Verilator.public(CombInit(that))
- val valid = patch(isFireing)
+ val valid = patch(isFireing && !IS_IO && (!NEED_TRANSLATION || !tpk.REDO && !tpk.PAGE_FAULT))
  val isLoad = patch(stage(IS_LOAD))
  val address = patch(stage(ADDRESS_TRANSLATED))
  val readData = patch(rspFormated)
@@ -1162,7 +1162,7 @@ class Lsu2Plugin(var lqSize: Int,
  }
  fpuWriteSize := SIZE
 
- LOAD_WRITE_FAILURE := IS_LOAD && specialOverride && !IS_IO
+ LOAD_WRITE_FAILURE := IS_LOAD && specialOverride && !IS_IO // IS_IO ??
 
 
  MISS_ALIGNED := (1 to log2Up(wordWidth/8)).map(i => SIZE === i && ADDRESS_PRE_TRANSLATION(i-1 downto 0) =/= 0).orR
@@ -1466,7 +1466,9 @@ class Lsu2Plugin(var lqSize: Int,
  prefetch.predictor.io.learn.allocate := True
  } otherwise {
  sq.ptr.onFree.valid := True
- whitebox.valid := True
+ when(!delayed.last.io) {
+ whitebox.valid := True
+ }
  }
  }
 
@@ -1744,11 +1746,11 @@ class Lsu2Plugin(var lqSize: Int,
  val valid = Verilator.public(False)
  val robIdV = Verilator.public(robId)
  val storeData = Verilator.public(alu.result)
+ val skipIt = Verilator.public(!reservationHit && storeSc)
  }
 
  ALU whenIsActive{
  result := alu.result
- storeWhitebox.valid := True
  goto(COMPLETION)
  }
 
@@ -1757,6 +1759,7 @@ class Lsu2Plugin(var lqSize: Int,
  comp.rfWrite := storeSc && sq.mem.writeRd
  }
  COMPLETION whenIsActive{
+ storeWhitebox.valid := True
  setup.specialCompletion.valid := True
  comp.wakeRf := False
  comp.rfWrite := False

diff --git a/src/main/scala/naxriscv/platform/NaxRiscvTilelink.scala b/src/main/scala/naxriscv/platform/NaxRiscvTilelink.scala
@@ -437,13 +437,14 @@ class NaxSimProbe(nax : NaxRiscv, hartId : Int){
  ctx.loadData = lsuWb.readData.toLong
  ctx.loadLqId = lsuWb.lqId.toInt
  backends.foreach(_.loadExecute(hartId, ctx.loadLqId, ctx.lsuAddress, ctx.lsuLen, ctx.loadData))
+ } else {
+ ctx.storeValid = true
  }
  }
  if(aguWbValid.toBoolean){
  val robId = aguWb.robId.toInt
  val ctx = robArray(robId)
  if(!aguWb.load.toBoolean) {
- ctx.storeValid = true
  ctx.storeSqId = (aguWb.aguId.toInt) % lsuPlugin.sqSize
  ctx.storeData = aguWb.data.toLong
  }
@@ -468,9 +469,8 @@ class NaxSimProbe(nax : NaxRiscv, hartId : Int){
  val robId = amoStoreWb.robIdV.toInt
  val ctx = robArray(robId)
 
- ctx.storeValid = true
+ ctx.storeValid = !amoStoreWb.skipIt.toBoolean
  ctx.storeData = amoStoreWb.storeData.toLong
- println("asd")
  }
  }
 
@@ -622,34 +622,34 @@ object NaxRiscvTilelinkSim extends App{
  memAgent.mem.randOffset = 0x80000000l
  val peripheralAgent = new PeripheralEmulator(dut.peripheral.emulated.node.bus, dut.peripheral.custom.mei, dut.peripheral.custom.sei, cd)
 
- val elf = new Elf(new File("ext/NaxSoftware/baremetal/dhrystone/build/rv32ima/dhrystone.elf"))
-// val elf = new Elf(new File("ext/NaxSoftware/baremetal/coremark/build/rv32ima/coremark.elf"))
-// val elf = new Elf(new File("ext/NaxSoftware/baremetal/freertosDemo/build/rv32ima/freertosDemo.elf"))
+//// val elf = new Elf(new File("ext/NaxSoftware/baremetal/dhrystone/build/rv32ima/dhrystone.elf"))
+//// val elf = new Elf(new File("ext/NaxSoftware/baremetal/coremark/build/rv32ima/coremark.elf"))
+//// val elf = new Elf(new File("ext/NaxSoftware/baremetal/freertosDemo/build/rv32ima/freertosDemo.elf"))
 // val elf = new Elf(new File("ext/NaxSoftware/baremetal/play/build/rv32ima/play.elf"))
-// val elf = new Elf(new File("ext/NaxSoftware/baremetal/machine/build/rv32ima/machine.elf"))
-// val elf = new Elf(new File("ext/NaxSoftware/baremetal/supervisor/build/rv32ima/supervisor.elf"))
-// val elf = new Elf(new File("ext/NaxSoftware/baremetal/mmu_sv32/build/rv32ima/mmu_sv32.elf"))
-
- elf.load(memAgent.mem, -0xffffffff80000000l)
- tracer.loadElf(0, elf.f)
- tracer.setPc(0, 0x80000000)
- val passSymbol = elf.getSymbolAddress("pass")
- val failSymbol = elf.getSymbolAddress("fail")
- naxProbe.commitsCallbacks += { (hartId, pc) =>
- if(pc == passSymbol) delayed(1)(simSuccess())
- if(pc == failSymbol) delayed(1)(simFailure())
- }
-
-// memAgent.mem.loadBin(0x00000000l, "ext/NaxSoftware/buildroot/images/rv32ima/fw_jump.bin")
-// memAgent.mem.loadBin(0x00F80000l, "ext/NaxSoftware/buildroot/images/rv32ima/linux.dtb")
-// memAgent.mem.loadBin(0x00400000l, "ext/NaxSoftware/buildroot/images/rv32ima/Image")
-// memAgent.mem.loadBin(0x01000000l, "ext/NaxSoftware/buildroot/images/rv32ima/rootfs.cpio")
+//// val elf = new Elf(new File("ext/NaxSoftware/baremetal/machine/build/rv32ima/machine.elf"))
+//// val elf = new Elf(new File("ext/NaxSoftware/baremetal/supervisor/build/rv32ima/supervisor.elf"))
+//// val elf = new Elf(new File("ext/NaxSoftware/baremetal/mmu_sv32/build/rv32ima/mmu_sv32.elf"))
 //
-// tracer.loadBin(0x80000000l, new File("ext/NaxSoftware/buildroot/images/rv32ima/fw_jump.bin"))
-// tracer.loadBin(0x80F80000l, new File("ext/NaxSoftware/buildroot/images/rv32ima/linux.dtb"))
-// tracer.loadBin(0x80400000l, new File("ext/NaxSoftware/buildroot/images/rv32ima/Image"))
-// tracer.loadBin(0x81000000l, new File("ext/NaxSoftware/buildroot/images/rv32ima/rootfs.cpio"))
+// elf.load(memAgent.mem, -0xffffffff80000000l)
+// tracer.loadElf(0, elf.f)
 // tracer.setPc(0, 0x80000000)
+// val passSymbol = elf.getSymbolAddress("pass")
+// val failSymbol = elf.getSymbolAddress("fail")
+// naxProbe.commitsCallbacks += { (hartId, pc) =>
+// if(pc == passSymbol) delayed(1)(simSuccess())
+// if(pc == failSymbol) delayed(1)(simFailure())
+// }
+
+ memAgent.mem.loadBin(0x00000000l, "ext/NaxSoftware/buildroot/images/rv32ima/fw_jump.bin")
+ memAgent.mem.loadBin(0x00F80000l, "ext/NaxSoftware/buildroot/images/rv32ima/linux.dtb")
+ memAgent.mem.loadBin(0x00400000l, "ext/NaxSoftware/buildroot/images/rv32ima/Image")
+ memAgent.mem.loadBin(0x01000000l, "ext/NaxSoftware/buildroot/images/rv32ima/rootfs.cpio")
+
+ tracer.loadBin(0x80000000l, new File("ext/NaxSoftware/buildroot/images/rv32ima/fw_jump.bin"))
+ tracer.loadBin(0x80F80000l, new File("ext/NaxSoftware/buildroot/images/rv32ima/linux.dtb"))
+ tracer.loadBin(0x80400000l, new File("ext/NaxSoftware/buildroot/images/rv32ima/Image"))
+ tracer.loadBin(0x81000000l, new File("ext/NaxSoftware/buildroot/images/rv32ima/rootfs.cpio"))
+ tracer.setPc(0, 0x80000000)
 
  cd.waitSampling(2000000)
  simSuccess()