Fix lsu LQ lock, and much refractoring, got 4 core to boot linux and …

…run user space terminal in sim

src/main/scala/naxriscv/lsu/DataCache.scala

@@ -710,6 +710,7 @@ class DataCache(val p : DataCacheParameters) extends Component {
  val refillEvent = out Bool()
  val writebackEvent = out Bool()
  val writebackBusy = out Bool()
+ val tagEvent = out Bool()
  }
 
  val cpuWordWidth = cpuDataWidth
@@ -1031,14 +1032,22 @@ class DataCache(val p : DataCacheParameters) extends Component {
  }
 
  val ackSender = withCoherency generate new Area{
+ val ack = cloneOf(io.mem.read.ack)
  val requests = slots.map(_.ackValid)
  val oh = OHMasking.first(requests)
- io.mem.read.ack.valid := requests.orR
- io.mem.read.ack.ackId := OhMux.or(oh, slots.map(_.ackId))
- when(io.mem.read.ack.ready){
+ ack.valid := requests.orR
+ ack.ackId := OhMux.or(oh, slots.map(_.ackId))
+ when(ack.ready){
  io.refillCompletions.asBools.onMask(oh)(_ := True)
  slots.onMask(oh)(_.ackValid := False)
  }
+
+ val buffer = ack.m2sPipe()
+ val counter = Reg(UInt(2 bits)) init(0)
+ when(buffer.valid){
+ counter := counter + 1
+ }
+ io.mem.read.ack << buffer.haltWhen(counter =/= 3) //Give some time for the CPU to do forward progress
  }
  }
 
@@ -1819,4 +1828,5 @@ class DataCache(val p : DataCacheParameters) extends Component {
 // }
  io.refillEvent := refill.push.valid
  io.writebackEvent := writeback.push.valid
+ io.tagEvent := waysWrite.mask.orR
 }

src/main/scala/naxriscv/lsu2/Lsu2Plugin.scala

@@ -468,11 +468,16 @@ class Lsu2Plugin(var lqSize: Int,
  val kill = False
  val valid = Reg(Bool()) init(False) clearWhen(kill)
  val address = Reg(UInt(PHYSICAL_WIDTH bits))
-
+ val tagsEvent = cache.withCoherency generate new Area {
+ val checkIt = RegNext(False) init (False)
+ val hadIt = History(cache.logic.cache.io.tagEvent, (1 to sharedCtrlAt - sharedFeedAt+1)).orR
+ kill setWhen (checkIt && hadIt)
+ }
  def spawn(value : UInt): Unit ={
  valid := True
  address := value
  counter := 0
+ tagsEvent.checkIt := True
  }
 
  val counter = Reg(UInt(7 bits)) init(0) //Give the reservation a 64 cycle life
@@ -980,7 +985,7 @@ class Lsu2Plugin(var lqSize: Int,
  cmd.virtual := ADDRESS_PRE_TRANSLATION
  cmd.size := SIZE
  cmd.redoOnDataHazard := False
- cmd.unique := IS_LOAD.mux[Bool](LR, AMO)
+ cmd.unique := !IS_LOAD || LR
 
  haltIt(!cmd.ready)
  }